Core part of riccardom cleanup patch 2200793
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2d5f11508d
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@ -161,11 +161,11 @@ int NDS_Init( void) {
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gfx3d_init();
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#ifdef GDB_STUB
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#ifdef GDB_STUB
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armcpu_new(&NDS_ARM7,1, arm7_mem_if, arm7_ctrl_iface);
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armcpu_new(&NDS_ARM9,0, arm9_mem_if, arm9_ctrl_iface);
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#else
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armcpu_new(&NDS_ARM7,1);
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armcpu_new(&NDS_ARM7,1);
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armcpu_new(&NDS_ARM9,0);
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#endif
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@ -6721,8 +6721,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2()
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OP_L_IA(13, start);
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OP_L_IA(14, start);
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if(BIT15(i))
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if(BIT15(i) == 0)
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{
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armcpu_switchMode(cpu, oldmode);
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}
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else
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{
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u32 tmp = READ32(cpu->mem_if->data, start);
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Status_Reg SPSR;
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cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
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@ -6730,13 +6735,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2()
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armcpu_switchMode(cpu, SPSR.bits.mode);
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cpu->CPSR=SPSR;
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//start += 4;
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cpu->next_instruction = cpu->R[15];
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cpu->next_instruction = cpu->R[15];
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c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
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}
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else
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{
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armcpu_switchMode(cpu, oldmode);
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}
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return c + 2;
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}
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@ -6778,7 +6779,11 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2()
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OP_L_IB(13, start);
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OP_L_IB(14, start);
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if(BIT15(i))
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if(BIT15(i) == 0)
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{
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armcpu_switchMode(cpu, oldmode);
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}
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else
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{
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u32 tmp;
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Status_Reg SPSR;
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@ -6791,10 +6796,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2()
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cpu->next_instruction = registres[15];
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c += waitState[(start>>24)&0xF];
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}
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else
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{
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armcpu_switchMode(cpu, oldmode);
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}
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return c + 2;
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}
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