diff --git a/desmume/src/NDSSystem.cpp b/desmume/src/NDSSystem.cpp index 8f6fcfcbf..495f0fdce 100644 --- a/desmume/src/NDSSystem.cpp +++ b/desmume/src/NDSSystem.cpp @@ -161,11 +161,11 @@ int NDS_Init( void) { gfx3d_init(); - #ifdef GDB_STUB +#ifdef GDB_STUB armcpu_new(&NDS_ARM7,1, arm7_mem_if, arm7_ctrl_iface); armcpu_new(&NDS_ARM9,0, arm9_mem_if, arm9_ctrl_iface); #else - armcpu_new(&NDS_ARM7,1); + armcpu_new(&NDS_ARM7,1); armcpu_new(&NDS_ARM9,0); #endif diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index 2fb0608ef..401452b9c 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -6721,8 +6721,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2() OP_L_IA(13, start); OP_L_IA(14, start); - if(BIT15(i)) + if(BIT15(i) == 0) { + armcpu_switchMode(cpu, oldmode); + } + else + { + u32 tmp = READ32(cpu->mem_if->data, start); Status_Reg SPSR; cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); @@ -6730,13 +6735,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2() armcpu_switchMode(cpu, SPSR.bits.mode); cpu->CPSR=SPSR; //start += 4; - cpu->next_instruction = cpu->R[15]; + cpu->next_instruction = cpu->R[15]; c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; } - else - { - armcpu_switchMode(cpu, oldmode); - } return c + 2; } @@ -6778,7 +6779,11 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2() OP_L_IB(13, start); OP_L_IB(14, start); - if(BIT15(i)) + if(BIT15(i) == 0) + { + armcpu_switchMode(cpu, oldmode); + } + else { u32 tmp; Status_Reg SPSR; @@ -6791,10 +6796,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2() cpu->next_instruction = registres[15]; c += waitState[(start>>24)&0xF]; } - else - { - armcpu_switchMode(cpu, oldmode); - } return c + 2; }