ShuriZma
/
desmume
mirror of https://github.com/TASEmulators/desmume.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Core part of riccardom cleanup patch 2200793

This commit is contained in:
yabause 2008-10-31 14:05:30 +00:00
parent 2d5f11508d
commit 95139a8bfa
2 changed files with 14 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
desmume/src/NDSSystem.cpp
View File

@ -161,11 +161,11 @@ int NDS_Init( void) {
gfx3d_init(); gfx3d_init();
#ifdef GDB_STUB #ifdef GDB_STUB
armcpu_new(&NDS_ARM7,1, arm7_mem_if, arm7_ctrl_iface); armcpu_new(&NDS_ARM7,1, arm7_mem_if, arm7_ctrl_iface);
armcpu_new(&NDS_ARM9,0, arm9_mem_if, arm9_ctrl_iface); armcpu_new(&NDS_ARM9,0, arm9_mem_if, arm9_ctrl_iface);
#else #else
armcpu_new(&NDS_ARM7,1); armcpu_new(&NDS_ARM7,1);
armcpu_new(&NDS_ARM9,0); armcpu_new(&NDS_ARM9,0);
#endif #endif

23
desmume/src/arm_instructions.cpp
View File

@ -6721,8 +6721,13 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2()
OP_L_IA(13, start); OP_L_IA(13, start);
OP_L_IA(14, start); OP_L_IA(14, start);
if(BIT15(i)) if(BIT15(i) == 0)
{ {
armcpu_switchMode(cpu, oldmode);
}
else
{
u32 tmp = READ32(cpu->mem_if->data, start); u32 tmp = READ32(cpu->mem_if->data, start);
Status_Reg SPSR; Status_Reg SPSR;
cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1)); cpu->R[15] = tmp & (0XFFFFFFFC | (BIT0(tmp)<<1));
@ -6730,13 +6735,9 @@ TEMPLATE static u32 FASTCALL OP_LDMIA2()
armcpu_switchMode(cpu, SPSR.bits.mode); armcpu_switchMode(cpu, SPSR.bits.mode);
cpu->CPSR=SPSR; cpu->CPSR=SPSR;
//start += 4; //start += 4;
cpu->next_instruction = cpu->R[15]; cpu->next_instruction = cpu->R[15];
c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF]; c += MMU.MMU_WAIT32[cpu->proc_ID][(start>>24)&0xF];
} }
else
{
armcpu_switchMode(cpu, oldmode);
}
return c + 2; return c + 2;
} }
@ -6778,7 +6779,11 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2()
OP_L_IB(13, start); OP_L_IB(13, start);
OP_L_IB(14, start); OP_L_IB(14, start);
if(BIT15(i)) if(BIT15(i) == 0)
{
armcpu_switchMode(cpu, oldmode);
}
else
{ {
u32 tmp; u32 tmp;
Status_Reg SPSR; Status_Reg SPSR;
@ -6791,10 +6796,6 @@ TEMPLATE static u32 FASTCALL OP_LDMIB2()
cpu->next_instruction = registres[15]; cpu->next_instruction = registres[15];
c += waitState[(start>>24)&0xF]; c += waitState[(start>>24)&0xF];
} }
else
{
armcpu_switchMode(cpu, oldmode);
}
return c + 2; return c + 2;
} }