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fix ff4 zoning bugs. its the SBCS/RSCS flags again. I reverted these to very ancient forms, in arm and thumb. Lets try it out for a while.

This commit is contained in:
zeromus 2009-02-14 22:28:32 +00:00
parent 842b39d1a6
commit 8dd437b984
2 changed files with 641 additions and 633 deletions
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11
desmume/src/arm_instructions.cpp
View File

@ -1320,6 +1320,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL()
OP_SBC(1, 3);
}
//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4
#define OP_SBCS(a, b) \
{ \
u32 tmp = v - (!cpu->CPSR.bits.C);\
@ -1335,11 +1336,12 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL()
}\
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp)) & (!UNSIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]));\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]);\
return a; \
}
TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM()
{
const u32 &i = cpu->instruction;
@ -1493,6 +1495,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL()
OP_RSC(1, 3);
}
//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4
#define OP_RSCS(a,b) \
{ \
u32 tmp = shift_op - (!cpu->CPSR.bits.C);\
@ -1508,8 +1511,8 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL()
}\
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp)) & (!UNSIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]));\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp) | SIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]);\
return a; \
}

67
desmume/src/thumb_instructions.cpp
View File

@ -1,27 +1,27 @@
/*
Copyright (C) 2006 yopyop
yopyop156@ifrance.com
yopyop156.ifrance.com
Copyright (C) 2006 yopyop
yopyop156@ifrance.com
yopyop156.ifrance.com
Code added on 18/08/2006 by shash
- Missing missaligned addresses correction
(reference in http://nocash.emubase.de/gbatek.htm#cpumemoryalignments)
Code added on 18/08/2006 by shash
- Missing missaligned addresses correction
(reference in http://nocash.emubase.de/gbatek.htm#cpumemoryalignments)
This file is part of DeSmuME
This file is part of DeSmuME
DeSmuME is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
DeSmuME is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
DeSmuME is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
DeSmuME is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with DeSmuME; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
You should have received a copy of the GNU General Public License
along with DeSmuME; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "bios.h"
@ -363,20 +363,25 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG()
cpu->CPSR.bits.N = BIT31(res);
cpu->CPSR.bits.Z = res == 0;
//the below UNSIGNED_UNDERFLOW calculation is the clever way of doing it
//but just to keep from making a mistake, lets assert that it matches the precise definition of unsigned overflow
static long passcount = 0;
assert(++passcount);
assert(
((((u64)a-(u64)b-(!cpu->CPSR.bits.C))>>32)&1)
== UNSIGNED_UNDERFLOW(a, b, res)
);
// //the below UNSIGNED_UNDERFLOW calculation is the clever way of doing it
// //but just to keep from making a mistake, lets assert that it matches the precise definition of unsigned overflow
// static long passcount = 0;
// assert(++passcount);
//assert(
// ((((u64)a-(u64)b-(!cpu->CPSR.bits.C))>>32)&1)
// == UNSIGNED_UNDERFLOW(a, b, res)
// );
//
// //zero 31-dec-2008 - apply normatt's fixed logic from the arm SBC instruction
// //although it seemed a bit odd to me and to whomever wrote this for SBC not to work similar to ADC..
// //but thats how it is.
// cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(a, b, res);
// cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, b, res);
//zero 14-feb-2009 - reverting this along with arm to old forms in order to fix zoning bug in ff4
cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(a, (u32)!cpu->CPSR.bits.C, tmp)) & (!UNSIGNED_OVERFLOW(tmp, b, res));
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, (u32)!cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(tmp, b, res);
//zero 31-dec-2008 - apply normatt's fixed logic from the arm SBC instruction
//although it seemed a bit odd to me and to whomever wrote this for SBC not to work similar to ADC..
//but thats how it is.
cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(a, b, res);
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, b, res);
return 3;
}