fix ff4 zoning bugs. its the SBCS/RSCS flags again. I reverted these to very ancient forms, in arm and thumb. Lets try it out for a while.
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@ -1320,6 +1320,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL()
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OP_SBC(1, 3);
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}
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//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4
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#define OP_SBCS(a, b) \
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{ \
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u32 tmp = v - (!cpu->CPSR.bits.C);\
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@ -1335,11 +1336,12 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL()
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}\
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
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cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp)) & (!UNSIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]));\
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]);\
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return a; \
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}
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TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM()
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{
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const u32 &i = cpu->instruction;
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@ -1493,6 +1495,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL()
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OP_RSC(1, 3);
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}
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//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4
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#define OP_RSCS(a,b) \
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{ \
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u32 tmp = shift_op - (!cpu->CPSR.bits.C);\
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@ -1508,8 +1511,8 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL()
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}\
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
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cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp)) & (!UNSIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]));\
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp) | SIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]);\
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return a; \
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}
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