fix ff4 zoning bugs. its the SBCS/RSCS flags again. I reverted these to very ancient forms, in arm and thumb. Lets try it out for a while.

This commit is contained in:
zeromus 2009-02-14 22:28:32 +00:00
parent 842b39d1a6
commit 8dd437b984
2 changed files with 641 additions and 633 deletions

View File

@ -1320,6 +1320,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL()
OP_SBC(1, 3);
}
//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4
#define OP_SBCS(a, b) \
{ \
u32 tmp = v - (!cpu->CPSR.bits.C);\
@ -1335,11 +1336,12 @@ TEMPLATE static u32 FASTCALL OP_SBC_IMM_VAL()
}\
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp)) & (!UNSIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]));\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, (u32)(!cpu->CPSR.bits.C), tmp) | SIGNED_UNDERFLOW(tmp, shift_op, cpu->R[REG_POS(i,12)]);\
return a; \
}
TEMPLATE static u32 FASTCALL OP_SBC_S_LSL_IMM()
{
const u32 &i = cpu->instruction;
@ -1493,6 +1495,7 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL()
OP_RSC(1, 3);
}
//zero 14-feb-2009 - reverting flag logic to fix zoning bug in ff4
#define OP_RSCS(a,b) \
{ \
u32 tmp = shift_op - (!cpu->CPSR.bits.C);\
@ -1508,8 +1511,8 @@ TEMPLATE static u32 FASTCALL OP_RSC_IMM_VAL()
}\
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
cpu->CPSR.bits.C = (!UNSIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp)) & (!UNSIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]));\
cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, (u32)(!cpu->CPSR.bits.C), (u32)tmp) | SIGNED_UNDERFLOW(tmp, v, cpu->R[REG_POS(i,12)]);\
return a; \
}

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