opps, forget a file
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mtabachenko
parent
243cadb4cd
commit
7a28e26a98
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@ -2444,11 +2444,58 @@ static int OP_CLZ(const u32 i)
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//-----------------------------------------------------------------------------
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// MCR / MRC
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//-----------------------------------------------------------------------------
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#define maskPrecalc \
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{ \
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X86CompilerFuncCall* ctxM = c.call((void*)maskPrecalc); \
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ctxM->setPrototype(ASMJIT_CALL_CONV, FuncBuilder0<Void>()); \
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// precalculate region masks/sets from cp15 register ----- JIT
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// TODO: rewrite to asm
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static void maskPrecalc(u32 _num)
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{
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#define precalc(num) { \
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u32 mask = 0, set = 0xFFFFFFFF ; /* (x & 0) == 0xFF..FF is allways false (disabled) */ \
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if (BIT_N(cp15.protectBaseSize[num],0)) /* if region is enabled */ \
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{ /* reason for this define: naming includes var */ \
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mask = CP15_MASKFROMREG(cp15.protectBaseSize[num]) ; \
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set = CP15_SETFROMREG(cp15.protectBaseSize[num]) ; \
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if (CP15_SIZEIDENTIFIER(cp15.protectBaseSize[num])==0x1F) \
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{ /* for the 4GB region, u32 suffers wraparound */ \
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mask = 0 ; set = 0 ; /* (x & 0) == 0 is allways true (enabled) */ \
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} \
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} \
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cp15.setSingleRegionAccess(num, mask, set) ; \
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}
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switch(_num)
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{
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case 0: precalc(0); break;
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case 1: precalc(1); break;
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case 2: precalc(2); break;
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case 3: precalc(3); break;
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case 4: precalc(4); break;
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case 5: precalc(5); break;
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case 6: precalc(6); break;
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case 7: precalc(7); break;
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case 0xFF:
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precalc(0);
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precalc(1);
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precalc(2);
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precalc(3);
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precalc(4);
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precalc(5);
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precalc(6);
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precalc(7);
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break;
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}
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#undef precalc
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}
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#define _maskPrecalc(num) \
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{ \
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GpVar _num = c.newGpVar(kX86VarTypeGpd); \
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X86CompilerFuncCall* ctxM = c.call((uintptr_t)maskPrecalc); \
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c.mov(_num, num); \
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ctxM->setPrototype(ASMJIT_CALL_CONV, FuncBuilder1<Void, u32>()); \
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ctxM->setArgument(0, _num); \
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}
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static int OP_MCR(const u32 i)
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{
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if (PROCNUM == ARMCPU_ARM7) return 0;
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@ -2548,12 +2595,12 @@ static int OP_MCR(const u32 i)
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case 2:
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//DaccessPerm = val;
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c.mov(cp15_ptr(DaccessPerm), data);
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maskPrecalc;
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_maskPrecalc(0xFF);
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break;
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case 3:
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//IaccessPerm = val;
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c.mov(cp15_ptr(IaccessPerm), data);
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maskPrecalc;
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_maskPrecalc(0xFF);
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break;
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default:
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bUnknown = true;
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@ -2565,50 +2612,11 @@ static int OP_MCR(const u32 i)
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case 6:
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if((opcode1==0) && (opcode2==0))
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{
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switch(CRm)
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if (CRm < 8)
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{
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case 0:
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//protectBaseSize0 = val;
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c.mov(cp15_ptr(protectBaseSize0), data);
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maskPrecalc;
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break;
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case 1:
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//protectBaseSize1 = val;
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c.mov(cp15_ptr(protectBaseSize1), data);
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maskPrecalc;
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break;
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case 2:
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//protectBaseSize2 = val;
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c.mov(cp15_ptr(protectBaseSize2), data);
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maskPrecalc;
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break;
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case 3:
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//protectBaseSize3 = val;
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c.mov(cp15_ptr(protectBaseSize3), data);
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maskPrecalc;
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break;
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case 4:
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//protectBaseSize4 = val;
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c.mov(cp15_ptr(protectBaseSize4), data);
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maskPrecalc;
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break;
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case 5:
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//protectBaseSize5 = val;
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c.mov(cp15_ptr(protectBaseSize5), data);
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maskPrecalc;
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break;
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case 6:
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//protectBaseSize6 = val;
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c.mov(cp15_ptr(protectBaseSize6), data);
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maskPrecalc;
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break;
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case 7:
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//protectBaseSize7 = val;
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c.mov(cp15_ptr(protectBaseSize7), data);
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maskPrecalc;
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break;
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default:
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bUnknown = true;
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//protectBaseSize[CRm] = val;
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c.mov(cp15_ptr(protectBaseSize[CRm]), data);
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_maskPrecalc(CRm);
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break;
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}
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}
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@ -2810,45 +2818,12 @@ static int OP_MRC(const u32 i)
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case 6:
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if((opcode1==0) && (opcode2==0))
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{
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switch(CRm)
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if (CRm < 8)
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{
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case 0:
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// *R = protectBaseSize0;
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c.mov(data, cp15_ptr(protectBaseSize0));
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break;
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case 1:
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// *R = protectBaseSize1;
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c.mov(data, cp15_ptr(protectBaseSize1));
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break;
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case 2:
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// *R = protectBaseSize2;
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c.mov(data, cp15_ptr(protectBaseSize2));
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break;
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case 3:
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// *R = protectBaseSize3;
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c.mov(data, cp15_ptr(protectBaseSize3));
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break;
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case 4:
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// *R = protectBaseSize4;
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c.mov(data, cp15_ptr(protectBaseSize4));
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break;
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case 5:
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// *R = protectBaseSize5;
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c.mov(data, cp15_ptr(protectBaseSize5));
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break;
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case 6:
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// *R = protectBaseSize6;
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c.mov(data, cp15_ptr(protectBaseSize6));
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break;
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case 7:
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// *R = protectBaseSize7;
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c.mov(data, cp15_ptr(protectBaseSize7));
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break;
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default:
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bUnknown = true;
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// *R = protectBaseSize[CRm];
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c.mov(data, cp15_ptr(protectBaseSize[CRm]));
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break;
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}
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break;
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}
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bUnknown = true;
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break;
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