JIT:
- fix OP_MCR (fix a delay boot M&L:PiT and SPP on x64 PGO build);
This commit is contained in:
mtabachenko
parent
8184770cd5
commit
243cadb4cd
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@ -2513,7 +2513,9 @@ void NDS_Reset()
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// only ARM9 have co-processor
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reconstruct(&cp15);
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cp15.reset(&NDS_ARM9);
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MMU.ARM9_RW_MODE = BIT7(cp15.ctrl);
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NDS_ARM9.intVector = 0xFFFF0000 * (BIT13(cp15.ctrl));
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NDS_ARM9.LDTBit = !BIT15(cp15.ctrl); //TBit
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resetUserInput();
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@ -1,6 +1,6 @@
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/*
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Copyright (C) 2006 yopyop
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Copyright (C) 2006-2011 DeSmuME team
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Copyright (C) 2006-2013 DeSmuME team
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This file is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -24,67 +24,11 @@
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armcp15_t cp15;
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bool armcp15_t::reset(armcpu_t * c)
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{
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//printf("CP15 Reset\n");
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cpu = c;
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IDCode = 0x41059461;
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cacheType = 0x0F0D2112;
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TCMSize = 0x00140180;
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ctrl = 0x00012078;
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DCConfig = 0x0;
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ICConfig = 0x0;
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writeBuffCtrl = 0x0;
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und = 0x0;
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DaccessPerm = 0x22222222;
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IaccessPerm = 0x22222222;
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protectBaseSize0 = 0x0;
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protectBaseSize1 = 0x0;
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protectBaseSize2 = 0x0;
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protectBaseSize3 = 0x0;
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protectBaseSize4 = 0x0;
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protectBaseSize5 = 0x0;
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protectBaseSize6 = 0x0;
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protectBaseSize7 = 0x0;
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cacheOp = 0x0;
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DcacheLock = 0x0;
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IcacheLock = 0x0;
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ITCMRegion = 0x0C;
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DTCMRegion = 0x0080000A;
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processID = 0;
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MMU.ARM9_RW_MODE = BIT7(ctrl);
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cpu->intVector = 0xFFFF0000 * (BIT13(ctrl));
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cpu->LDTBit = !BIT15(ctrl); //TBit
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/* preset calculated regionmasks */
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for (u8 i=0;i<8;i++) {
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regionWriteMask_USR[i] = 0 ;
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regionWriteMask_SYS[i] = 0 ;
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regionReadMask_USR[i] = 0 ;
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regionReadMask_SYS[i] = 0 ;
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regionExecuteMask_USR[i] = 0 ;
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regionExecuteMask_SYS[i] = 0 ;
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regionWriteSet_USR[i] = 0 ;
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regionWriteSet_SYS[i] = 0 ;
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regionReadSet_USR[i] = 0 ;
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regionReadSet_SYS[i] = 0 ;
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regionExecuteSet_USR[i] = 0 ;
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regionExecuteSet_SYS[i] = 0 ;
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} ;
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return true;
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}
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#define ACCESSTYPE(val,n) (((val) >> (4*n)) & 0x0F)
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#define SIZEIDENTIFIER(val) ((((val) >> 1) & 0x1F))
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#define SIZEBINARY(val) (1 << (SIZEIDENTIFIER(val)+1))
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#define MASKFROMREG(val) (~((SIZEBINARY(val)-1) | 0x3F))
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#define SETFROMREG(val) ((val) & MASKFROMREG(val))
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#define CP15_ACCESSTYPE(val, n) (((val) >> (4*n)) & 0x0F)
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/* sets the precalculated regions to mask,set for the affected accesstypes */
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void armcp15_t::setSingleRegionAccess(u32 dAccess,u32 iAccess,unsigned char num, u32 mask,u32 set) {
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void armcp15_t::setSingleRegionAccess(u8 num, u32 mask, u32 set) {
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switch (ACCESSTYPE(dAccess,num)) {
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switch (CP15_ACCESSTYPE(DaccessPerm, num)) {
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case 4: /* UNP */
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case 7: /* UNP */
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case 8: /* UNP */
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@ -156,7 +100,7 @@ void armcp15_t::setSingleRegionAccess(u32 dAccess,u32 iAccess,unsigned char num,
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regionReadSet_SYS[num] = set ;
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break ;
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}
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switch (ACCESSTYPE(iAccess,num)) {
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switch (CP15_ACCESSTYPE(IaccessPerm, num)) {
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case 4: /* UNP */
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case 7: /* UNP */
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case 8: /* UNP */
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@ -195,16 +139,16 @@ void armcp15_t::maskPrecalc()
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{
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#define precalc(num) { \
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u32 mask = 0, set = 0xFFFFFFFF ; /* (x & 0) == 0xFF..FF is allways false (disabled) */ \
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if (BIT_N(protectBaseSize##num,0)) /* if region is enabled */ \
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if (BIT_N(protectBaseSize[num],0)) /* if region is enabled */ \
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{ /* reason for this define: naming includes var */ \
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mask = MASKFROMREG(protectBaseSize##num) ; \
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set = SETFROMREG(protectBaseSize##num) ; \
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if (SIZEIDENTIFIER(protectBaseSize##num)==0x1F) \
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mask = CP15_MASKFROMREG(protectBaseSize[num]) ; \
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set = CP15_SETFROMREG(protectBaseSize[num]) ; \
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if (CP15_SIZEIDENTIFIER(protectBaseSize[num])==0x1F) \
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{ /* for the 4GB region, u32 suffers wraparound */ \
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mask = 0 ; set = 0 ; /* (x & 0) == 0 is allways true (enabled) */ \
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} \
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} \
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setSingleRegionAccess(DaccessPerm,IaccessPerm,num,mask,set) ; \
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setSingleRegionAccess(num, mask, set) ; \
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}
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precalc(0) ;
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precalc(1) ;
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@ -267,12 +211,7 @@ BOOL armcp15_t::store(u8 CRd, u8 adr)
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BOOL armcp15_t::moveCP2ARM(u32 * R, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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{
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if (!cpu)
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{
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printf("ERROR: cp15 don\'t allocated\n");
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return FALSE;
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}
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if(cpu->CPSR.bits.mode == USR) return FALSE;
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if(NDS_ARM9.CPSR.bits.mode == USR) return FALSE;
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switch(CRn)
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{
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@ -345,34 +284,10 @@ BOOL armcp15_t::moveCP2ARM(u32 * R, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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case 6:
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if((opcode1==0) && (opcode2==0))
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{
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switch(CRm)
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if (CRm < 8)
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{
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case 0:
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*R = protectBaseSize0;
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*R = protectBaseSize[CRm];
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return TRUE;
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case 1:
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*R = protectBaseSize1;
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return TRUE;
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case 2:
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*R = protectBaseSize2;
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return TRUE;
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case 3:
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*R = protectBaseSize3;
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return TRUE;
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case 4:
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*R = protectBaseSize4;
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return TRUE;
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case 5:
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*R = protectBaseSize5;
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return TRUE;
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case 6:
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*R = protectBaseSize6;
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return TRUE;
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case 7:
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*R = protectBaseSize7;
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return TRUE;
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default:
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return FALSE;
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}
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}
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return FALSE;
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@ -416,12 +331,7 @@ BOOL armcp15_t::moveCP2ARM(u32 * R, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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BOOL armcp15_t::moveARM2CP(u32 val, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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{
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if (!cpu)
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{
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printf("ERROR: cp15 don\'t allocated\n");
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return FALSE;
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}
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if(cpu->CPSR.bits.mode == USR) return FALSE;
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if(NDS_ARM9.CPSR.bits.mode == USR) return FALSE;
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switch(CRn)
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{
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@ -433,8 +343,8 @@ BOOL armcp15_t::moveARM2CP(u32 val, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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ctrl = (val & 0x000FF085) | 0x00000078;
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MMU.ARM9_RW_MODE = BIT7(val);
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//zero 31-jan-2010: change from 0x0FFF0000 to 0xFFFF0000 per gbatek
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cpu->intVector = 0xFFFF0000 * (BIT13(val));
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cpu->LDTBit = !BIT15(val); //TBit
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NDS_ARM9.intVector = 0xFFFF0000 * (BIT13(val));
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NDS_ARM9.LDTBit = !BIT15(val); //TBit
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//LOG("CP15: ARMtoCP ctrl %08X (val %08X)\n", ctrl, val);
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return TRUE;
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}
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@ -484,42 +394,11 @@ BOOL armcp15_t::moveARM2CP(u32 val, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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case 6:
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if((opcode1==0) && (opcode2==0))
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{
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switch(CRm)
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if (CRm < 8)
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{
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case 0:
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protectBaseSize0 = val;
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protectBaseSize[CRm] = val;
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maskPrecalc();
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return TRUE;
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case 1:
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protectBaseSize1 = val;
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maskPrecalc();
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return TRUE;
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case 2:
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protectBaseSize2 = val;
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maskPrecalc();
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return TRUE;
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case 3:
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protectBaseSize3 = val;
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maskPrecalc();
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return TRUE;
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case 4:
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protectBaseSize4 = val;
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maskPrecalc();
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return TRUE;
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case 5:
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protectBaseSize5 = val;
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maskPrecalc();
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return TRUE;
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case 6:
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protectBaseSize6 = val;
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maskPrecalc();
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return TRUE;
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case 7:
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protectBaseSize7 = val;
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maskPrecalc();
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return TRUE;
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default:
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return FALSE;
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}
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}
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return FALSE;
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@ -527,8 +406,8 @@ BOOL armcp15_t::moveARM2CP(u32 val, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2)
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if((CRm==0)&&(opcode1==0)&&((opcode2==4)))
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{
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//CP15wait4IRQ;
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cpu->waitIRQ = TRUE;
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cpu->halt_IE_and_IF = TRUE;
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NDS_ARM9.waitIRQ = TRUE;
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NDS_ARM9.halt_IE_and_IF = TRUE;
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//IME set deliberately omitted: only SWI sets IME to 1
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return TRUE;
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}
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@ -585,14 +464,7 @@ void armcp15_t::saveone(EMUFILE* os)
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write32le(und,os);
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write32le(DaccessPerm,os);
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write32le(IaccessPerm,os);
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write32le(protectBaseSize0,os);
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write32le(protectBaseSize1,os);
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write32le(protectBaseSize2,os);
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write32le(protectBaseSize3,os);
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write32le(protectBaseSize4,os);
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write32le(protectBaseSize5,os);
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write32le(protectBaseSize6,os);
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write32le(protectBaseSize7,os);
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for(int i=0;i<8;i++) write32le(protectBaseSize[i],os);
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write32le(cacheOp,os);
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write32le(DcacheLock,os);
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write32le(IcacheLock,os);
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@ -628,14 +500,7 @@ bool armcp15_t::loadone(EMUFILE* is)
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if(!read32le(&und,is)) return false;
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if(!read32le(&DaccessPerm,is)) return false;
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if(!read32le(&IaccessPerm,is)) return false;
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if(!read32le(&protectBaseSize0,is)) return false;
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if(!read32le(&protectBaseSize1,is)) return false;
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if(!read32le(&protectBaseSize2,is)) return false;
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if(!read32le(&protectBaseSize3,is)) return false;
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if(!read32le(&protectBaseSize4,is)) return false;
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if(!read32le(&protectBaseSize5,is)) return false;
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if(!read32le(&protectBaseSize6,is)) return false;
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if(!read32le(&protectBaseSize7,is)) return false;
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for(int i=0;i<8;i++) if(!read32le(&protectBaseSize[i],is)) return false;
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if(!read32le(&cacheOp,is)) return false;
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if(!read32le(&DcacheLock,is)) return false;
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if(!read32le(&IcacheLock,is)) return false;
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@ -660,31 +525,3 @@ bool armcp15_t::loadone(EMUFILE* is)
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return true;
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}
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/* precalculate region masks/sets from cp15 register ----- JIT */
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void maskPrecalc()
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{
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#define precalc(num) { \
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u32 mask = 0, set = 0xFFFFFFFF ; /* (x & 0) == 0xFF..FF is allways false (disabled) */ \
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if (BIT_N(cp15.protectBaseSize##num,0)) /* if region is enabled */ \
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{ /* reason for this define: naming includes var */ \
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mask = MASKFROMREG(cp15.protectBaseSize##num) ; \
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set = SETFROMREG(cp15.protectBaseSize##num) ; \
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if (SIZEIDENTIFIER(cp15.protectBaseSize##num)==0x1F) \
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{ /* for the 4GB region, u32 suffers wraparound */ \
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mask = 0 ; set = 0 ; /* (x & 0) == 0 is allways true (enabled) */ \
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} \
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} \
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cp15.setSingleRegionAccess(cp15.DaccessPerm,cp15.IaccessPerm,num,mask,set) ; \
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}
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precalc(0) ;
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precalc(1) ;
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precalc(2) ;
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precalc(3) ;
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precalc(4) ;
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precalc(5) ;
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precalc(6) ;
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precalc(7) ;
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#undef precalc
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}
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@ -1,6 +1,6 @@
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/*
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Copyright (C) 2006 yopyop
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Copyright (C) 2006-2010 DeSmuME team
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Copyright (C) 2006-2013 DeSmuME team
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This file is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -32,6 +32,11 @@
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#define CP15_ACCESS_EXECUSR CP15_ACCESS_EXECUTE
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#define CP15_ACCESS_EXECSYS 5
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#define CP15_SIZEBINARY(val) (1 << (CP15_SIZEIDENTIFIER(val)+1))
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#define CP15_SIZEIDENTIFIER(val) ((((val) >> 1) & 0x1F))
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#define CP15_MASKFROMREG(val) (~((CP15_SIZEBINARY(val)-1) | 0x3F))
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#define CP15_SETFROMREG(val) ((val) & CP15_MASKFROMREG(val))
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struct armcp15_t
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{
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public:
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@ -45,14 +50,7 @@ public:
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u32 und;
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u32 DaccessPerm;
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u32 IaccessPerm;
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u32 protectBaseSize0;
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u32 protectBaseSize1;
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u32 protectBaseSize2;
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u32 protectBaseSize3;
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u32 protectBaseSize4;
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u32 protectBaseSize5;
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u32 protectBaseSize6;
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u32 protectBaseSize7;
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u32 protectBaseSize[8];
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u32 cacheOp;
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u32 DcacheLock;
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u32 IcacheLock;
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@ -77,41 +75,32 @@ public:
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u32 regionExecuteSet_USR[8] ;
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u32 regionExecuteSet_SYS[8] ;
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armcpu_t *cpu;
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void setSingleRegionAccess(u32 dAccess,u32 iAccess,unsigned char num, u32 mask,u32 set);
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void setSingleRegionAccess(u8 num, u32 mask, u32 set);
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void maskPrecalc();
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public:
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armcp15_t() : IDCode(0),
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cacheType(0),
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TCMSize(0),
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ctrl(0),
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armcp15_t() : IDCode(0x41059461),
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cacheType(0x0F0D2112),
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TCMSize(0x00140180),
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ctrl(0x00012078),
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DCConfig(0),
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ICConfig(0),
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writeBuffCtrl(0),
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und(0),
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DaccessPerm(0),
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IaccessPerm(0),
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protectBaseSize0(0),
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protectBaseSize1(0),
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protectBaseSize2(0),
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protectBaseSize3(0),
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protectBaseSize4(0),
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protectBaseSize5(0),
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protectBaseSize6(0),
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protectBaseSize7(0),
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DaccessPerm(0x22222222),
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IaccessPerm(0x22222222),
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cacheOp(0),
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DcacheLock(0),
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IcacheLock(0),
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ITCMRegion(0),
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DTCMRegion(0),
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ITCMRegion(0x0C),
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DTCMRegion(0x0080000A),
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processID(0),
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RAM_TAG(0),
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testState(0),
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cacheDbg(0),
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cpu(NULL)
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cacheDbg(0)
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{
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//printf("CP15 Reset\n");
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memset(&protectBaseSize[0], 0, sizeof(protectBaseSize));
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memset(®ionWriteMask_USR[0], 0, sizeof(regionWriteMask_USR));
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memset(®ionWriteMask_SYS[0], 0, sizeof(regionWriteMask_SYS));
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memset(®ionReadMask_USR[0], 0, sizeof(regionReadMask_USR));
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@ -125,7 +114,6 @@ public:
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memset(®ionExecuteSet_USR[0], 0, sizeof(regionExecuteSet_USR));
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memset(®ionExecuteSet_SYS[0], 0, sizeof(regionExecuteSet_SYS));
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}
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bool reset(armcpu_t * c);
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BOOL dataProcess(u8 CRd, u8 CRn, u8 CRm, u8 opcode1, u8 opcode2);
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BOOL load(u8 CRd, u8 adr);
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BOOL store(u8 CRd, u8 adr);
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@ -138,5 +126,4 @@ public:
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};
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extern armcp15_t cp15;
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void maskPrecalc();
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#endif /* __CP15_H__*/
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