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desmume
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i dont understand why the gdb stub needs these things, but we'll leave them for now.

This commit is contained in:
zeromus 2010-05-01 18:36:13 +00:00
parent 6a9bd1be82
commit 6cf0fff5d4
2 changed files with 29 additions and 29 deletions
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16
desmume/src/NDSSystem.cpp
View File

@ -1936,11 +1936,11 @@ void execHardware_interrupts()
{ {
if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0])) if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0]))
{ {
//#ifdef GDB_STUB #ifdef GDB_STUB
// if ( armcpu_flagIrq( &NDS_ARM9)) if ( armcpu_flagIrq( &NDS_ARM9))
//#else #else
if ( armcpu_irqException(&NDS_ARM9)) if ( armcpu_irqException(&NDS_ARM9))
//#endif #endif
{ {
//printf("ARM9 interrupt! flags: %08X ; mask: %08X ; result: %08X\n",MMU.reg_IF[0],MMU.reg_IE[0],MMU.reg_IF[0]&MMU.reg_IE[0]); //printf("ARM9 interrupt! flags: %08X ; mask: %08X ; result: %08X\n",MMU.reg_IF[0],MMU.reg_IE[0],MMU.reg_IF[0]&MMU.reg_IE[0]);
//nds.ARM9Cycle = nds.cycles; //nds.ARM9Cycle = nds.cycles;
@ -1949,11 +1949,11 @@ void execHardware_interrupts()
if((MMU.reg_IF[1]&MMU.reg_IE[1]) && (MMU.reg_IME[1])) if((MMU.reg_IF[1]&MMU.reg_IE[1]) && (MMU.reg_IME[1]))
{ {
//#ifdef GDB_STUB #ifdef GDB_STUB
// if ( armcpu_flagIrq( &NDS_ARM7)) if ( armcpu_flagIrq( &NDS_ARM7))
//#else #else
if ( armcpu_irqException(&NDS_ARM7)) if ( armcpu_irqException(&NDS_ARM7))
//#endif #endif
{ {
//nds.ARM7Cycle = nds.cycles; //nds.ARM7Cycle = nds.cycles;
} }

42
desmume/src/armcpu.cpp
View File

@ -474,44 +474,44 @@ BOOL armcpu_irqException(armcpu_t *armcpu)
if(armcpu->CPSR.bits.I) return FALSE; if(armcpu->CPSR.bits.I) return FALSE;
//#ifdef GDB_STUB #ifdef GDB_STUB
// armcpu->irq_flag = 0; armcpu->irq_flag = 0;
//#endif #endif
tmp = armcpu->CPSR; tmp = armcpu->CPSR;
armcpu_switchMode(armcpu, IRQ); armcpu_switchMode(armcpu, IRQ);
//#ifdef GDB_STUB #ifdef GDB_STUB
// armcpu->R[14] = armcpu->next_instruction + 4; armcpu->R[14] = armcpu->next_instruction + 4;
//#else #else
armcpu->R[14] = armcpu->instruct_adr + 4; armcpu->R[14] = armcpu->instruct_adr + 4;
//#endif #endif
armcpu->SPSR = tmp; armcpu->SPSR = tmp;
armcpu->CPSR.bits.T = 0; armcpu->CPSR.bits.T = 0;
armcpu->CPSR.bits.I = 1; armcpu->CPSR.bits.I = 1;
armcpu->next_instruction = armcpu->intVector + 0x18; armcpu->next_instruction = armcpu->intVector + 0x18;
armcpu->waitIRQ = 0; armcpu->waitIRQ = 0;
//#ifndef GDB_STUB #ifndef GDB_STUB
armcpu->R[15] = armcpu->next_instruction + 8; armcpu->R[15] = armcpu->next_instruction + 8;
armcpu_prefetch(armcpu); armcpu_prefetch(armcpu);
//#endif #endif
return TRUE; return TRUE;
} }
//BOOL BOOL
//armcpu_flagIrq( armcpu_t *armcpu) { armcpu_flagIrq( armcpu_t *armcpu) {
// if(armcpu->CPSR.bits.I) return FALSE; if(armcpu->CPSR.bits.I) return FALSE;
//
// armcpu->waitIRQ = 0; armcpu->waitIRQ = 0;
//
//#ifdef GDB_STUB #ifdef GDB_STUB
// armcpu->irq_flag = 1; armcpu->irq_flag = 1;
//#endif #endif
//
// return TRUE; return TRUE;
//} }
template<int PROCNUM> template<int PROCNUM>
u32 armcpu_exec() u32 armcpu_exec()