Fix the overflow flag on thumb SUB opcodes (this could also affect other opcodes).
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7b4b78b215
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@ -305,9 +305,9 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM3(const u32 i)
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cpu->R[REG_NUM(i, 0)] = Rn - imm3;
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.Z = cpu->R[REG_NUM(i, 0)] == 0;
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
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cpu->CPSR.bits.C = !BorrowFrom(Rn, imm3);
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cpu->CPSR.bits.V = OverflowFromSUB(REG_NUM(i, 0), Rn, imm3);
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(Rn,imm3,cpu->R[REG_NUM(i, 0)]);
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return 1;
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}
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@ -321,7 +321,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_IMM8(const u32 i)
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 8)]);
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 8)] == 0);
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cpu->CPSR.bits.C = !BorrowFrom(Rd, imm8);
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cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_NUM(i, 8)], Rd, imm8);
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(Rd,imm8,cpu->R[REG_NUM(i, 8)]);
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return 1;
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}
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@ -335,7 +335,7 @@ TEMPLATE static u32 FASTCALL OP_SUB_REG(const u32 i)
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
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cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
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cpu->CPSR.bits.C = !BorrowFrom(Rn, Rm);
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cpu->CPSR.bits.V = OverflowFromSUB(cpu->R[REG_NUM(i, 0)], Rn, Rm);
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(Rn,Rm,cpu->R[REG_NUM(i, 0)]);
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return 1;
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}
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