MMU : preparing big cleanup (use #define USE_OLD 0 in MMU.c to help me with that)
This commit is contained in:
damdoum
parent
5442bf1d78
commit
549e1f72cb
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@ -512,20 +512,21 @@ extern GraphicsInterface_struct GFXDummy;
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void GPU_setVideoProp(GPU *, u32 p);
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void GPU_setVideoProp(GPU *, u32 p);
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void GPU_setBGProp(GPU *, u16 num, u16 p);
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void GPU_setBGProp(GPU *, u16 num, u16 p);
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void GPU_scrollX(GPU *, u8 num, u16 v);
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void GPU_scrollX(GPU *, u8 num, u16 v);
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void GPU_scrollY(GPU *, u8 num, u16 v);
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void GPU_scrollY(GPU *, u8 num, u16 v);
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void GPU_scrollXY(GPU *, u8 num, u32 v);
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void GPU_setX(GPU *, u8 num, u32 v);
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void GPU_setXH(GPU *, u8 num, u16 v);
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void GPU_setXH(GPU *, u8 num, u16 v);
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void GPU_setXL(GPU *, u8 num, u16 v);
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void GPU_setXL(GPU *, u8 num, u16 v);
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void GPU_setY(GPU *, u8 num, u32 v);
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void GPU_setYH(GPU *, u8 num, u16 v);
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void GPU_setYH(GPU *, u8 num, u16 v);
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void GPU_setYL(GPU *, u8 num, u16 v);
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void GPU_setYL(GPU *, u8 num, u16 v);
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void GPU_setPA(GPU *, u8 num, u16 v);
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void GPU_setPA(GPU *, u8 num, u16 v);
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void GPU_setPB(GPU *, u8 num, u16 v);
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void GPU_setPB(GPU *, u8 num, u16 v);
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void GPU_setPC(GPU *, u8 num, u16 v);
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void GPU_setPC(GPU *, u8 num, u16 v);
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void GPU_setPD(GPU *, u8 num, u16 v);
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void GPU_setPD(GPU *, u8 num, u16 v);
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void GPU_scrollXY(GPU *, u8 num, u32 v);
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void GPU_setX(GPU *, u8 num, u32 v);
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void GPU_setY(GPU *, u8 num, u32 v);
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void GPU_setPAPB(GPU *, u8 num, u32 v);
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void GPU_setPAPB(GPU *, u8 num, u32 v);
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void GPU_setPCPD(GPU *, u8 num, u32 v);
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void GPU_setPCPD(GPU *, u8 num, u32 v);
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1474
desmume/src/MMU.c
1474
desmume/src/MMU.c
File diff suppressed because it is too large
Load Diff
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@ -25,38 +25,41 @@
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static u16 vx=0,vy=0,vz=0;
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static u16 vx=0,vy=0,vz=0;
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//#define print(a) printf a
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#define print(a)
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INLINE void gl_VTX_one() {
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INLINE void gl_VTX_one() {
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float vfx,vfy,vfz;
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float vfx,vfy,vfz;
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vfx = vx / 4096.;
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vfx = vx / 4096.;
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vfy = vy / 4096.;
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vfy = vy / 4096.;
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vfz = vz / 4096.;
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vfz = vz / 4096.;
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printf ("\tVTX (x=%.12f,y=%.12f,z=%.12f)\n",vfx,vfy,vfz);
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print(("\tVTX (x=%.12f,y=%.12f,z=%.12f)\n",vfx,vfy,vfz));
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}
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}
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void gl_VTX_begin(u32 val) {
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void gl_VTX_begin(u32 val) {
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//see 4000500h - Cmd 40h - BEGIN_VTXS - Start of Vertex List (W)
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//see 4000500h - Cmd 40h - BEGIN_VTXS - Start of Vertex List (W)
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vx=vy=vz=0;
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vx=vy=vz=0;
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printf ("VTX_begin : ");
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print(("VTX_begin : "));
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switch(val) {
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switch(val) {
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case 0 : // separate triangles (3 vertices for each triangle)
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case 0 : // separate triangles (3 vertices for each triangle)
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printf ("GL_TRIANGLES\n");
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print(("GL_TRIANGLES\n"));
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break;
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break;
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case 1 : // separate quads (4 vertices for each triangle)
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case 1 : // separate quads (4 vertices for each triangle)
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printf ("GL_QUADS\n");
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print(("GL_QUADS\n"));
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break;
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break;
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// strips : 1st triangle or quad defined by all vertices
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// strips : 1st triangle or quad defined by all vertices
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// next ones share a segment (so 2 vertices less)
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// next ones share a segment (so 2 vertices less)
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case 2 : // triangle strips (1st : 3, next : 1)
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case 2 : // triangle strips (1st : 3, next : 1)
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printf ("GL_TRIANGLE_STRIP\n");
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print(("GL_TRIANGLE_STRIP\n"));
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break;
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break;
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case 3 : // quad strips (1st : 4, next : 2)
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case 3 : // quad strips (1st : 4, next : 2)
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printf ("GL_QUAD_STRIP\n");
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print(("GL_QUAD_STRIP\n"));
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break;
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break;
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}
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}
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}
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}
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void gl_VTX_end() {
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void gl_VTX_end() {
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//see 4000504h - Cmd 41h - END_VTXS - End of Vertex List (W)
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//see 4000504h - Cmd 41h - END_VTXS - End of Vertex List (W)
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printf ("VTX_end.\n");
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print(("VTX_end.\n"));
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}
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}
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@ -1,52 +1,66 @@
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#ifndef REGISTERS_H
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#ifndef REGISTERS_H
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#define REGISTERS_H
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#define REGISTERS_H
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// Display Engine A
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#define REG_REGION_MASK 0x0FFFEF80
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#define REG_DISPA_DISPCNT 0x04000000
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#define REG_BASE_DISPx 0x04000000
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#define REG_BASE_DISPA 0x04000000
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#define REG_BASE_DISPB 0x04001000
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#define REG_BASE_DMA 0x04000080
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#define REG_BASE_SIORTCTIMERS 0x04000100
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#define REG_BASE_ROMIPC 0x04000180
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#define REG_BASE_MEMIRQ 0x04000200
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#define REG_BASE_MATH 0x04000280
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#define REG_BASE_OTHER 0x04000300
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#define REG_BASE_RCVPORTS 0x04100000
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#define REG_DISPB 0x00001000
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// core A and B specific
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#define REG_DISPx_DISPCNT 0x04000000
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#define REG_DISPx_VCOUNT 0x04000006
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#define REG_DISPx_BG0CNT 0x04000008
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#define REG_DISPx_BG1CNT 0x0400000A
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#define REG_DISPx_BG2CNT 0x0400000C
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#define REG_DISPx_BG3CNT 0x0400000E
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#define REG_DISPx_BG0HOFS 0x04000010
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#define REG_DISPx_BG0VOFS 0x04000012
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#define REG_DISPx_BG1HOFS 0x04000014
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#define REG_DISPx_BG1VOFS 0x04000016
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#define REG_DISPx_BG2HOFS 0x04000018
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#define REG_DISPx_BG2VOFS 0x0400001A
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#define REG_DISPx_BG3HOFS 0x0400001C
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#define REG_DISPx_BG3VOFS 0x0400001E
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#define REG_DISPx_BG2PA 0x04000020
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#define REG_DISPx_BG2PB 0x04000022
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#define REG_DISPx_BG2PC 0x04000024
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#define REG_DISPx_BG2PD 0x04000026
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#define REG_DISPx_BG2XL 0x04000028
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#define REG_DISPx_BG2XH 0x0400002A
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#define REG_DISPx_BG2YL 0x0400002C
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#define REG_DISPx_BG2YH 0x0400002E
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#define REG_DISPx_BG3PA 0x04000030
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#define REG_DISPx_BG3PB 0x04000032
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#define REG_DISPx_BG3PC 0x04000034
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#define REG_DISPx_BG3PD 0x04000036
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#define REG_DISPx_BG3XL 0x04000038
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#define REG_DISPx_BG3XH 0x0400003A
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#define REG_DISPx_BG3YL 0x0400003C
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#define REG_DISPx_BG3YH 0x0400003E
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#define REG_DISPx_WIN0H 0x04000040
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#define REG_DISPx_WIN1H 0x04000042
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#define REG_DISPx_WIN0V 0x04000044
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#define REG_DISPx_WIN1V 0x04000046
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#define REG_DISPx_WININ 0x04000048
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#define REG_DISPx_WINOUT 0x0400004A
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#define REG_DISPx_MOSAIC 0x0400004C
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#define REG_DISPx_BLDCNT 0x04000050
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#define REG_DISPx_BLDALPHA 0x04000052
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#define REG_DISPx_BLDY 0x04000054
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#define REG_DISPx_MASTERBRIGHT 0x0400006C
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// core A specific
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#define REG_DISPA_DISPSTAT 0x04000004
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#define REG_DISPA_DISPSTAT 0x04000004
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#define REG_DISPA_VCOUNT 0x04000006
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#define REG_DISPA_BG0CNT 0x04000008
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#define REG_DISPA_BG1CNT 0x0400000A
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#define REG_DISPA_BG2CNT 0x0400000C
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#define REG_DISPA_BG3CNT 0x0400000E
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#define REG_DISPA_BG0HOFS 0x04000010
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#define REG_DISPA_BG0VOFS 0x04000012
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#define REG_DISPA_BG1HOFS 0x04000014
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#define REG_DISPA_BG1VOFS 0x04000016
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#define REG_DISPA_BG2HOFS 0x04000018
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#define REG_DISPA_BG2VOFS 0x0400001A
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#define REG_DISPA_BG3HOFS 0x0400001C
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#define REG_DISPA_BG3VOFS 0x0400001E
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#define REG_DISPA_BG2PA 0x04000020
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#define REG_DISPA_BG2PB 0x04000022
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#define REG_DISPA_BG2PC 0x04000024
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#define REG_DISPA_BG2PD 0x04000026
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#define REG_DISPA_BG2XL 0x04000028
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#define REG_DISPA_BG2XH 0x0400002A
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#define REG_DISPA_BG2YL 0x0400002C
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#define REG_DISPA_BG2YH 0x0400002E
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#define REG_DISPA_BG3PA 0x04000030
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#define REG_DISPA_BG3PB 0x04000032
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#define REG_DISPA_BG3PC 0x04000034
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#define REG_DISPA_BG3PD 0x04000036
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#define REG_DISPA_BG3XL 0x04000038
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#define REG_DISPA_BG3XH 0x0400003A
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#define REG_DISPA_BG3YL 0x0400003C
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#define REG_DISPA_BG3YH 0x0400003E
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#define REG_DISPA_WIN0H 0x04000040
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#define REG_DISPA_WIN1H 0x04000042
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#define REG_DISPA_WIN0V 0x04000044
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#define REG_DISPA_WIN1V 0x04000046
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#define REG_DISPA_WININ 0x04000048
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#define REG_DISPA_WINOUT 0x0400004A
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#define REG_DISPA_MOSAIC 0x0400004C
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#define REG_DISPA_BLDCNT 0x04000050
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#define REG_DISPA_BLDALPHA 0x04000052
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#define REG_DISPA_BLDY 0x04000054
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#define REG_DISPA_DISP3DCNT 0x04000060
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#define REG_DISPA_DISP3DCNT 0x04000060
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#define REG_DISPA_DISPCAPCNT 0x04000064
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#define REG_DISPA_DISPCAPCNT 0x04000064
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#define REG_DISPA_DISPMMEMFIFO 0x04000068
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#define REG_DISPA_DISPMMEMFIFO 0x04000068
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#define REG_DISPA_MASTERBRIGHT 0x0400006C
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// DMA
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// DMA
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#define REG_DMA0SAD 0x040000B0
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#define REG_DMA0SAD 0x040000B0
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@ -142,47 +156,6 @@
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#define REG_POWCNT2 0x04000304
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#define REG_POWCNT2 0x04000304
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#define REG_BIOSPROT 0x04000308
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#define REG_BIOSPROT 0x04000308
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#define REG_DISPB_DISPCNT 0x04001000
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#define REG_DISPB_BG0CNT 0x04001008
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#define REG_DISPB_BG1CNT 0x0400100A
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#define REG_DISPB_BG2CNT 0x0400100C
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#define REG_DISPB_BG3CNT 0x0400100E
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#define REG_DISPB_BG0HOFS 0x04001010
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#define REG_DISPB_BG0VOFS 0x04001012
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#define REG_DISPB_BG1HOFS 0x04001014
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#define REG_DISPB_BG1VOFS 0x04001016
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#define REG_DISPB_BG2HOFS 0x04001018
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#define REG_DISPB_BG2VOFS 0x0400101A
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#define REG_DISPB_BG3HOFS 0x0400101C
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#define REG_DISPB_BG3VOFS 0x0400101E
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#define REG_DISPB_BG2PA 0x04001020
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#define REG_DISPB_BG2PB 0x04001022
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#define REG_DISPB_BG2PC 0x04001024
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#define REG_DISPB_BG2PD 0x04001026
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#define REG_DISPB_BG2XL 0x04001028
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#define REG_DISPB_BG2XH 0x0400102A
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#define REG_DISPB_BG2YL 0x0400102C
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#define REG_DISPB_BG2YH 0x0400102E
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#define REG_DISPB_BG3PA 0x04001030
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#define REG_DISPB_BG3PB 0x04001032
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#define REG_DISPB_BG3PC 0x04001034
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#define REG_DISPB_BG3PD 0x04001036
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#define REG_DISPB_BG3XL 0x04001038
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#define REG_DISPB_BG3XH 0x0400103A
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#define REG_DISPB_BG3YL 0x0400103C
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#define REG_DISPB_BG3YH 0x0400103E
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#define REG_DISPB_WIN0H 0x04001040
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#define REG_DISPB_WIN1H 0x04001042
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#define REG_DISPB_WIN0V 0x04001044
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#define REG_DISPB_WIN1V 0x04001046
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#define REG_DISPB_WININ 0x04001048
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#define REG_DISPB_WINOUT 0x0400104A
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#define REG_DISPB_MOSAIC 0x0400104C
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#define REG_DISPB_BLDCNT 0x04001050
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#define REG_DISPB_BLDALPHA 0x04001052
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#define REG_DISPB_BLDY 0x04001054
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#define REG_DISPB_MASTERBRIGHT 0x0400106C
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// Receive ports
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// Receive ports
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#define REG_IPCFIFORECV 0x04100000
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#define REG_IPCFIFORECV 0x04100000
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#define REG_GCDATAIN 0x04100010
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#define REG_GCDATAIN 0x04100010
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@ -282,9 +282,9 @@ int savestate_load (const char *file_name) {
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MMU_write16(ARMCPU_ARM9, 0x04000304, MMU_read16(ARMCPU_ARM9, 0x04000304));
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MMU_write16(ARMCPU_ARM9, 0x04000304, MMU_read16(ARMCPU_ARM9, 0x04000304));
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// This should regenerate the graphics configuration
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// This should regenerate the graphics configuration
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for (i = REG_DISPA_DISPCNT; i<=REG_DISPA_MASTERBRIGHT; i+=2)
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for (i = REG_BASE_DISPA; i<=REG_BASE_DISPA + 0x7F; i+=2)
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MMU_write16(ARMCPU_ARM9, i, MMU_read16(ARMCPU_ARM9, i));
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MMU_write16(ARMCPU_ARM9, i, MMU_read16(ARMCPU_ARM9, i));
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for (i = REG_DISPB_DISPCNT; i<=REG_DISPB_MASTERBRIGHT; i+=2)
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for (i = REG_BASE_DISPB; i<=REG_BASE_DISPB + 0x7F; i+=2)
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MMU_write16(ARMCPU_ARM9, i, MMU_read16(ARMCPU_ARM9, i));
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MMU_write16(ARMCPU_ARM9, i, MMU_read16(ARMCPU_ARM9, i));
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gzclose (file);
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gzclose (file);
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