diff --git a/desmume/src/GPU.h b/desmume/src/GPU.h index ee7927401..67c36eba1 100644 --- a/desmume/src/GPU.h +++ b/desmume/src/GPU.h @@ -512,20 +512,21 @@ extern GraphicsInterface_struct GFXDummy; void GPU_setVideoProp(GPU *, u32 p); void GPU_setBGProp(GPU *, u16 num, u16 p); + void GPU_scrollX(GPU *, u8 num, u16 v); void GPU_scrollY(GPU *, u8 num, u16 v); -void GPU_scrollXY(GPU *, u8 num, u32 v); - -void GPU_setX(GPU *, u8 num, u32 v); void GPU_setXH(GPU *, u8 num, u16 v); void GPU_setXL(GPU *, u8 num, u16 v); -void GPU_setY(GPU *, u8 num, u32 v); void GPU_setYH(GPU *, u8 num, u16 v); void GPU_setYL(GPU *, u8 num, u16 v); void GPU_setPA(GPU *, u8 num, u16 v); void GPU_setPB(GPU *, u8 num, u16 v); void GPU_setPC(GPU *, u8 num, u16 v); void GPU_setPD(GPU *, u8 num, u16 v); + +void GPU_scrollXY(GPU *, u8 num, u32 v); +void GPU_setX(GPU *, u8 num, u32 v); +void GPU_setY(GPU *, u8 num, u32 v); void GPU_setPAPB(GPU *, u8 num, u32 v); void GPU_setPCPD(GPU *, u8 num, u32 v); diff --git a/desmume/src/MMU.c b/desmume/src/MMU.c index 4c985c9cc..58f494987 100644 --- a/desmume/src/MMU.c +++ b/desmume/src/MMU.c @@ -21,6 +21,8 @@ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + +#define USE_OLD 1 //#define RENDER3D #include @@ -46,6 +48,8 @@ char szRomPath[512]; char szRomBaseName[512]; +u16 partie = 1; + #define DUP2(x) x, x #define DUP4(x) x, x, x, x @@ -771,40 +775,1153 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr) /* Returns data from memory */ return T1ReadLong(MMU.MMU_MEM[proc][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[proc][(adr >> 20) & 0xFF]); } + + + + + +INLINE void MMU_write8_REG_VRAMCNT(u32 adr, u8 val) { + // nbbytes = 1 + int slot; + switch(adr) { + case REG_VRAMCNTA: + case REG_VRAMCNTB: + case REG_VRAMCNTC: + case REG_VRAMCNTD: + MMU_VRAMWriteBackToLCD(0) ; + MMU_VRAMWriteBackToLCD(1) ; + MMU_VRAMWriteBackToLCD(2) ; + MMU_VRAMWriteBackToLCD(3) ; + switch(val & 0x1F) + { + case 1 : + MMU.vram_mode[adr-REG_VRAMCNTA] = 0; // BG-VRAM + //MMU.vram_offset[0] = ARM9Mem.ARM9_ABG+(0x20000*0); // BG-VRAM + break; + case 1 | (1 << 3) : + MMU.vram_mode[adr-REG_VRAMCNTA] = 1; // BG-VRAM + //MMU.vram_offset[0] = ARM9Mem.ARM9_ABG+(0x20000*1); // BG-VRAM + break; + case 1 | (2 << 3) : + MMU.vram_mode[adr-REG_VRAMCNTA] = 2; // BG-VRAM + //MMU.vram_offset[0] = ARM9Mem.ARM9_ABG+(0x20000*2); // BG-VRAM + break; + case 1 | (3 << 3) : + MMU.vram_mode[adr-REG_VRAMCNTA] = 3; // BG-VRAM + //MMU.vram_offset[0] = ARM9Mem.ARM9_ABG+(0x20000*3); // BG-VRAM + break; + case 0: /* mapped to lcd */ + MMU.vram_mode[adr-REG_VRAMCNTA] = 4 | (adr-REG_VRAMCNTA) ; + break ; + } + MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTA,val) ; + break; + case REG_VRAMCNTE : + MMU_VRAMWriteBackToLCD(REG_VRAMCNTE) ; + if((val & 7) == 5) + { + ARM9Mem.ExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x80000; + ARM9Mem.ExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x82000; + ARM9Mem.ExtPal[0][2] = ARM9Mem.ARM9_LCD + 0x84000; + ARM9Mem.ExtPal[0][3] = ARM9Mem.ARM9_LCD + 0x86000; + } + else if((val & 7) == 3) + { + ARM9Mem.texPalSlot[0] = ARM9Mem.ARM9_LCD + 0x80000; + ARM9Mem.texPalSlot[1] = ARM9Mem.ARM9_LCD + 0x82000; + ARM9Mem.texPalSlot[2] = ARM9Mem.ARM9_LCD + 0x84000; + ARM9Mem.texPalSlot[3] = ARM9Mem.ARM9_LCD + 0x86000; + } + else if((val & 7) == 4) + { + ARM9Mem.ExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x80000; + ARM9Mem.ExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x82000; + ARM9Mem.ExtPal[0][2] = ARM9Mem.ARM9_LCD + 0x84000; + ARM9Mem.ExtPal[0][3] = ARM9Mem.ARM9_LCD + 0x86000; + } -void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) -{ - if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion)) - { - /* Writes data in DTCM (ARM9 only) */ - ARM9Mem.ARM9_DTCM[adr&0x3FFF] = val; - return ; + MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTE,val) ; + break; + + case REG_VRAMCNTF : + slot = (val>>3)&0x3; + switch(val & 0x7) + { + case 4 : + ARM9Mem.ExtPal[0][slot] = ARM9Mem.ARM9_LCD + 0x90000; + ARM9Mem.ExtPal[0][slot+1] = ARM9Mem.ARM9_LCD + 0x92000; + break; + case 3 : + ARM9Mem.texPalSlot[slot] = ARM9Mem.ARM9_LCD + 0x90000; + break; + case 5 : + ARM9Mem.ObjExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x90000; + ARM9Mem.ObjExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x92000; + break; + } + break; + case REG_VRAMCNTG : + slot = (val>>3)&0x3; + switch(val & 0x7) + { + case 4 : + ARM9Mem.ExtPal[0][slot] = ARM9Mem.ARM9_LCD + 0x94000; + ARM9Mem.ExtPal[0][slot+1] = ARM9Mem.ARM9_LCD + 0x96000; + break; + case 3 : + ARM9Mem.texPalSlot[slot] = ARM9Mem.ARM9_LCD + 0x94000; + break; + case 5 : + ARM9Mem.ObjExtPal[0][0] = ARM9Mem.ARM9_LCD + 0x94000; + ARM9Mem.ObjExtPal[0][1] = ARM9Mem.ARM9_LCD + 0x96000; + break; + } + break; + + case REG_VRAMCNTH : + MMU_VRAMWriteBackToLCD(REG_VRAMCNTH) ; + + if((val & 7) == 2) + { + ARM9Mem.ExtPal[1][0] = ARM9Mem.ARM9_LCD + 0x98000; + ARM9Mem.ExtPal[1][1] = ARM9Mem.ARM9_LCD + 0x9A000; + ARM9Mem.ExtPal[1][2] = ARM9Mem.ARM9_LCD + 0x9C000; + ARM9Mem.ExtPal[1][3] = ARM9Mem.ARM9_LCD + 0x9E000; + } + + MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTH,val) ; + break; + + case REG_VRAMCNTI : + MMU_VRAMWriteBackToLCD(REG_VRAMCNTI) ; + + if((val & 7) == 3) + { + ARM9Mem.ObjExtPal[1][0] = ARM9Mem.ARM9_LCD + 0xA0000; + ARM9Mem.ObjExtPal[1][1] = ARM9Mem.ARM9_LCD + 0xA2000; + } + + MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTI,val) ; + break; } +} + +INLINE void MMU_write16_REG_DISPx(u32 adr, u16 val) { + + GPU * gpu; + if (adr & REG_DISPB) + gpu = SubScreen.gpu; + else + gpu = MainScreen.gpu; + + + switch(adr & ~REG_DISPB) { + + case REG_DISPx_BG0CNT : + //GPULOG("MAIN BG0 SETPROP 16B %08X\r\n", val); + GPU_setBGProp(gpu, 0, val); + break; + case REG_DISPx_BG1CNT : + //GPULOG("MAIN BG1 SETPROP 16B %08X\r\n", val); + GPU_setBGProp(gpu, 1, val); + break; + case REG_DISPx_BG2CNT : + //GPULOG("MAIN BG2 SETPROP 16B %08X\r\n", val); + GPU_setBGProp(gpu, 2, val); + break; + case REG_DISPx_BG3CNT : + //GPULOG("MAIN BG3 SETPROP 16B %08X\r\n", val); + GPU_setBGProp(gpu, 3, val); + break; + case REG_DISPx_BG0HOFS : + GPU_scrollX(gpu, 0, val); + break; + case REG_DISPx_BG0VOFS : + GPU_scrollY(gpu, 0, val); + break; + case REG_DISPx_BG1HOFS : + GPU_scrollX(gpu, 1, val); + break; + case REG_DISPx_BG1VOFS : + GPU_scrollY(gpu, 1, val); + break; + case REG_DISPx_BG2HOFS : + GPU_scrollX(gpu, 2, val); + break; + case REG_DISPx_BG2VOFS : + GPU_scrollY(gpu, 2, val); + break; + case REG_DISPx_BG3HOFS : + GPU_scrollX(gpu, 3, val); + break; + case REG_DISPx_BG3VOFS : + GPU_scrollY(gpu, 3, val); + break; + case REG_DISPx_BG2PA : + GPU_setPA(gpu, 2, val); + break; + case REG_DISPx_BG2PB : + GPU_setPB(gpu, 2, val); + break; + case REG_DISPx_BG2PC : + GPU_setPC(gpu, 2, val); + break; + case REG_DISPx_BG2PD : + GPU_setPD(gpu, 2, val); + break; + case REG_DISPx_BG2XL : + GPU_setXL(gpu, 2, val); + break; + case REG_DISPx_BG2XH : + GPU_setXH(gpu, 2, val); + break; + case REG_DISPx_BG2YL : + GPU_setYL(gpu, 2, val); + break; + case REG_DISPx_BG2YH : + GPU_setYH(gpu, 2, val); + break; + case REG_DISPx_BG3PA : + GPU_setPA(gpu, 3, val); + break; + case REG_DISPx_BG3PB : + GPU_setPB(gpu, 3, val); + break; + case REG_DISPx_BG3PC : + GPU_setPC(gpu, 3, val); + break; + case REG_DISPx_BG3PD : + GPU_setPD(gpu, 3, val); + break; + case REG_DISPx_BG3XL : + GPU_setXL(gpu, 3, val); + break; + case REG_DISPx_BG3XH : + GPU_setXH(gpu, 3, val); + break; + case REG_DISPx_BG3YL : + GPU_setYL(gpu, 3, val); + break; + case REG_DISPx_BG3YH : + GPU_setYH(gpu, 3, val); + break; + case REG_DISPx_WIN0H: + GPU_setWINDOW_XDIM(gpu,val,0); + break; + case REG_DISPx_WIN1H: + GPU_setWINDOW_XDIM(gpu,val,1); + break; + case REG_DISPx_WIN0V: + GPU_setWINDOW_YDIM(gpu,val,0); + break; + case REG_DISPx_WIN1V: + GPU_setWINDOW_YDIM(gpu,val,1); + break; + case REG_DISPx_WININ: + GPU_setWINDOW_INCNT(gpu, val); + break; + case REG_DISPx_WINOUT: + GPU_setWINDOW_OUTCNT(gpu, val); + break; + case REG_DISPx_MOSAIC: + GPU_setMOSAIC(gpu,val); + break; + case REG_DISPx_BLDCNT: + GPU_setBLDCNT(gpu,val); + break; + case REG_DISPx_BLDALPHA: + GPU_setBLDALPHA(gpu,val); + break; + case REG_DISPx_BLDY: + GPU_setBLDY(gpu,val); + break; + case REG_DISPx_MASTERBRIGHT: + GPU_setMASTER_BRIGHT(gpu, val); + break; +#ifdef RENDER3D + case REG_DISPx_DISP3DCNT: + OGLRender::glControl(val); + break; +#endif + + } +} + + +INLINE void MMU_write32_REG_DISPx(u32 adr_u32, u32 val_u32) { + + GPU * gpu; + if (adr_u32 & REG_DISPB) + gpu = SubScreen.gpu; + else + gpu = MainScreen.gpu; + + switch(adr_u32) { + case REG_DISPx_DISPCNT : + case REG_DISPB | REG_DISPx_DISPCNT : + //execute = FALSE; + GPU_setVideoProp(gpu, val_u32); + break; + case REG_DISPA_DISPCAPCNT : + GPU_set_DISPCAPCNT(gpu,val_u32); + break; + case REG_DISPA_DISPMMEMFIFO: + // NOTE: right now, the capture unit is not taken into account, + // I don't know is it should be handled here or + + FIFOAdd(MMU.fifos + MAIN_MEMORY_DISP_FIFO, val_u32); + break; + } +} + + +INLINE void MMU_write32_REG_ROMIPC(u32 proc, u32 adr_u32, u32 val_u32) { + // address should be word aligned + switch(adr_u32) { + case REG_IPCSYNC : + { + //execute=FALSE; + u32 remote = proc^1; + u32 IPCSYNC_remote = T1ReadLong(MMU.MMU_MEM[remote][0x40], 0x180); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x180, (val_u32&0xFFF0)|((IPCSYNC_remote>>8)&0xF)); + T1WriteLong(MMU.MMU_MEM[remote][0x40], 0x180, (IPCSYNC_remote&0xFFF0)|((val_u32>>8)&0xF)); + MMU.reg_IF[remote] |= ((IPCSYNC_remote & (1<<14))<<2) & ((val_u32 & (1<<13))<<3);// & (MMU.reg_IME[remote] << 16);// & (MMU.reg_IE[remote] & (1<<16));// + } + break; + case REG_IPCFIFOCNT : + { + u32 cnt_l = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184) ; + u32 cnt_r = T1ReadWord(MMU.MMU_MEM[proc^1][0x40], 0x184) ; + if ((val_u32 & 0x8000) && !(cnt_l & 0x8000)) + { + /* this is the first init, the other side didnt init yet */ + /* so do a complete init */ + FIFOInit(MMU.fifos + (IPCFIFO+proc)); + T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184,0x8101) ; + /* and then handle it as usual */ + } + if(val_u32 & 0x4008) + { + FIFOInit(MMU.fifos + (IPCFIFO+(proc^1))); + T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, (cnt_l & 0x0301) | (val_u32 & 0x8404) | 1); + T1WriteWord(MMU.MMU_MEM[proc^1][0x40], 0x184, (cnt_r & 0xC507) | 0x100); + MMU.reg_IF[proc] |= ((val_u32 & 4)<<15);// & (MMU.reg_IME[proc]<<17);// & (MMU.reg_IE[proc]&0x20000);// + break; + } + T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, val_u32 & 0xBFF4); + //execute = FALSE; + } + break; + case REG_IPCFIFOSEND : + { + u16 IPCFIFO_CNT = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184); + if(IPCFIFO_CNT&0x8000) + { + //if(val_u32==43) execute = FALSE; + u32 remote = proc^1; + u32 fifonum = IPCFIFO+remote; + u16 IPCFIFO_CNT_remote; + FIFOAdd(MMU.fifos + fifonum, val_u32); + IPCFIFO_CNT = (IPCFIFO_CNT & 0xFFFC) | (MMU.fifos[fifonum].full<<1); + IPCFIFO_CNT_remote = T1ReadWord(MMU.MMU_MEM[remote][0x40], 0x184); + IPCFIFO_CNT_remote = (IPCFIFO_CNT_remote & 0xFCFF) | (MMU.fifos[fifonum].full<<10); + T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, IPCFIFO_CNT); + T1WriteWord(MMU.MMU_MEM[remote][0x40], 0x184, IPCFIFO_CNT_remote); + MMU.reg_IF[remote] |= ((IPCFIFO_CNT_remote & (1<<10))<<8);// & (MMU.reg_IME[remote] << 18);// & (MMU.reg_IE[remote] & 0x40000);// + //execute = FALSE; + } + } + break; + case REG_GCROMCTRL : + { + int i; + if (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB7) { + MMU.dscard[proc].adress = (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+1) << 24) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+2) << 16) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+3) << 8) | (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT+4)); + MMU.dscard[proc].transfer_count = 0x80;// * ((val_u32>>24)&7)); + + } else if (MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT) == 0xB8) { + // Get ROM chip ID + val_u32 |= 0x800000; // Data-Word Status + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val_u32); + MMU.dscard[proc].adress = 0; + + } else { + LOG("CARD command: %02X\n", MEM_8(MMU.MMU_MEM[proc], REG_GCCMDOUT)); + } + + //CARDLOG("%08X : %08X %08X\r\n", adr, val_u32, adresse[proc]); + val_u32 |= 0x00800000; + + if(MMU.dscard[proc].adress == 0) + { + val_u32 &= ~0x80000000; + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val_u32); + return; + } + + T1WriteLong(MMU.MMU_MEM[proc][(REG_GCROMCTRL >> 20) & 0xff], REG_GCROMCTRL & 0xfff, val_u32); + + /* launch DMA if start flag was set to "DS Cart" */ + if(proc == ARMCPU_ARM7) i = 2; + else i = 5; + + /* dma0/1 on arm7 can't start on ds cart event */ + if(proc == ARMCPU_ARM9 && MMU.DMAStartTime[proc][0] == i) { + MMU_doDMA(proc, 0); + + } else if(proc == ARMCPU_ARM9 && MMU.DMAStartTime[proc][1] == i) { + MMU_doDMA(proc, 1); + + } else if(MMU.DMAStartTime[proc][2] == i) { + MMU_doDMA(proc, 2); + + } else if(MMU.DMAStartTime[proc][3] == i) { + MMU_doDMA(proc, 3); + + } + } + break; + } +} + + +INLINE void MMU_write16_REG_SPI(u32 proc, u32 adr_u16, u16 val_u16) { + // address should be hword aligned + switch(adr_u16) { + case REG_AUXSPICNT: + T1WriteWord(MMU.MMU_MEM[proc][(REG_AUXSPICNT >> 20) & 0xff], REG_AUXSPICNT & 0xfff, val_u16); + AUX_SPI_CNT = val_u16; + + if (val_u16 == 0) + mc_reset_com(&MMU.bupmem); /* reset backup memory device communication */ + return; + case REG_AUXSPIDATA: + if(val_u16!=0) + { + AUX_SPI_CMD = val_u16 & 0xFF; + } + + T1WriteWord(MMU.MMU_MEM[proc][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val_u16)); + return; + case REG_SPICNT : + if(proc == ARMCPU_ARM7) + { + SPI_CNT = val_u16; + + //MMU.fw.com == 0; /* reset fw device communication */ + + mc_reset_com(&MMU.fw); /* reset fw device communication */ + } + + T1WriteWord(MMU.MMU_MEM[proc][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff, val_u16); + return; + + case REG_SPIDATA : + if(proc==ARMCPU_ARM7) + { + u16 spicnt; + + if(val_u16!=0) + { + SPI_CMD = val_u16; + } + + spicnt = T1ReadWord(MMU.MMU_MEM[proc][(REG_SPICNT >> 20) & 0xff], REG_SPICNT & 0xfff); + + switch((spicnt >> 8) & 0x3) + { + case 0 : + break; + + case 1 : /* firmware memory device */ + if(spicnt & 0x3 != 0) /* check SPI baudrate (must be 4mhz) */ + { + T1WriteWord(MMU.MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, 0); + break; + } + T1WriteWord(MMU.MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, fw_transfer(&MMU.fw, val_u16)); + return; + + case 2 : + switch(SPI_CMD & 0x70) + { + case 0x00 : + val_u16 = 0; + break; + case 0x10 : + //execute = FALSE; + if(SPI_CNT&(1<<11)) + { + if(partie) + { + val_u16 = ((nds.touchY<<3)&0x7FF); + partie = 0; + //execute = FALSE; + break; + } + val_u16 = (nds.touchY>>5); + partie = 1; + break; + } + val_u16 = ((nds.touchY<<3)&0x7FF); + partie = 1; + break; + case 0x20 : + val_u16 = 0; + break; + case 0x30 : + val_u16 = 0; + break; + case 0x40 : + val_u16 = 0; + break; + case 0x50 : + if(spicnt & 0x800) + { + if(partie) + { + val_u16 = ((nds.touchX<<3)&0x7FF); + partie = 0; + break; + } + val_u16 = (nds.touchX>>5); + partie = 1; + break; + } + val_u16 = ((nds.touchX<<3)&0x7FF); + partie = 1; + break; + case 0x60 : + val_u16 = 0; + break; + case 0x70 : + val_u16 = 0; + break; + } + break; + + case 3 : + /* NOTICE: Device 3 of SPI is reserved (unused and unusable) */ + break; + } + } + T1WriteWord(MMU.MMU_MEM[proc][(REG_SPIDATA >> 20) & 0xff], REG_SPIDATA & 0xfff, val_u16); + return; + } +} + + +INLINE void MMU_write32_REG_DMA(u32 proc, u32 adr, u32 val) { + switch(adr) { + case REG_DMA0CNTL : + //LOG("32 bit dma0 %04X\r\n", val); + DMASrc[proc][0] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xB0); + DMADst[proc][0] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xB4); + MMU.DMAStartTime[proc][0] = (proc ? (val>>28) & 0x3 : (val>>27) & 0x7); + MMU.DMACrt[proc][0] = val; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0xB8, val); + if( MMU.DMAStartTime[proc][0] == 0) // Start Immediately + MMU_doDMA(proc, 0); +#ifdef LOG_DMA2 + else + { + LOG("proc %d, dma %d src %08X dst %08X start taille %d %d\r\n", proc, 0, DMASrc[proc][0], DMADst[proc][0], 0, ((MMU.DMACrt[proc][0]>>27)&7)); + } +#endif + //execute = FALSE; + break; + case REG_DMA1CNTL : + //LOG("32 bit dma1 %04X\r\n", val); + DMASrc[proc][1] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xBC); + DMADst[proc][1] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xC0); + MMU.DMAStartTime[proc][1] = (proc ? (val>>28) & 0x3 : (val>>27) & 0x7); + MMU.DMACrt[proc][1] = val; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0xC4, val); + if(MMU.DMAStartTime[proc][1] == 0) // Start Immediately + MMU_doDMA(proc, 1); +#ifdef LOG_DMA2 + else + { + LOG("proc %d, dma %d src %08X dst %08X start taille %d %d\r\n", proc, 1, DMASrc[proc][1], DMADst[proc][1], 0, ((MMU.DMACrt[proc][1]>>27)&7)); + } +#endif + break; + case REG_DMA2CNTL : + //LOG("32 bit dma2 %04X\r\n", val); + DMASrc[proc][2] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xC8); + DMADst[proc][2] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xCC); + MMU.DMAStartTime[proc][2] = (proc ? (val>>28) & 0x3 : (val>>27) & 0x7); + MMU.DMACrt[proc][2] = val; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0xD0, val); + if(MMU.DMAStartTime[proc][2] == 0) // Start Immediately + MMU_doDMA(proc, 2); +#ifdef LOG_DMA2 + else + { + LOG("proc %d, dma %d src %08X dst %08X start taille %d %d\r\n", proc, 2, DMASrc[proc][2], DMADst[proc][2], 0, ((MMU.DMACrt[proc][2]>>27)&7)); + } +#endif + break; + case REG_DMA3CNTL : + //LOG("32 bit dma3 %04X\r\n", val); + DMASrc[proc][3] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xD4); + DMADst[proc][3] = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0xD8); + MMU.DMAStartTime[proc][3] = (proc ? (val>>28) & 0x3 : (val>>27) & 0x7); + MMU.DMACrt[proc][3] = val; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0xDC, val); + if( MMU.DMAStartTime[proc][3] == 0) // Start Immediately + MMU_doDMA(proc, 3); +#ifdef LOG_DMA2 + else + { + LOG("proc %d, dma %d src %08X dst %08X start taille %d %d\r\n", proc, 3, DMASrc[proc][3], DMADst[proc][3], 0, ((MMU.DMACrt[proc][3]>>27)&7)); + } +#endif + break; + } +} + +INLINE void MMU_write32_REG_MATH(u32 proc, u32 adr, u32 val) { + switch(adr) { + case REG_DIVDENOM : + { + u16 cnt; + s64 num = 0; + s64 den = 1; + s64 res; + s64 mod; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x298, val); + cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x280); + switch(cnt&3) + { + case 0: + { + num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290); + den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298); + } + break; + case 1: + { + num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290); + den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298); + } + break; + case 2: + { + return; + } + break; + default: + break; + } + if(den==0) + { + res = 0; + mod = 0; + cnt |= 0x4000; + cnt &= 0x7FFF; + } + else + { + res = num / den; + mod = num % den; + cnt &= 0x3FFF; + } + DIVLOG("BOUT1 %08X%08X / %08X%08X = %08X%08X\r\n", (u32)(num>>32), (u32)num, + (u32)(den>>32), (u32)den, + (u32)(res>>32), (u32)res); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A0, (u32) res); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A4, (u32) (res >> 32)); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A8, (u32) mod); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2AC, (u32) (mod >> 32)); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x280, cnt); + } + break; + case REG_DIVDENOM+4 : + { + u16 cnt; + s64 num = 0; + s64 den = 1; + s64 res; + s64 mod; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x29C, val); + cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x280); + switch(cnt&3) + { + case 0: + { + return; + } + break; + case 1: + { + return; + } + break; + case 2: + { + num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290); + den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298); + } + break; + default: + break; + } + if(den==0) + { + res = 0; + mod = 0; + cnt |= 0x4000; + cnt &= 0x7FFF; + } + else + { + res = num / den; + mod = num % den; + cnt &= 0x3FFF; + } + DIVLOG("BOUT2 %08X%08X / %08X%08X = %08X%08X\r\n", (u32)(num>>32), (u32)num, + (u32)(den>>32), (u32)den, + (u32)(res>>32), (u32)res); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A0, (u32) res); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A4, (u32) (res >> 32)); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A8, (u32) mod); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2AC, (u32) (mod >> 32)); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x280, cnt); + } + break; + case REG_SQRTPARAM : + { + u16 cnt; + u64 v = 1; + //execute = FALSE; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B8, val); + cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x2B0); + switch(cnt&1) + { + case 0: + v = (u64) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x2B8); + break; + case 1: + return; + } + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, (u32) sqrt(v)); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt & 0x7FFF); + SQRTLOG("BOUT1 sqrt(%08X%08X) = %08X\r\n", (u32)(v>>32), (u32)v, + T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x2B4)); + } + break; + case REG_SQRTPARAM+4 : + { + u16 cnt; + u64 v = 1; + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2BC, val); + cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x2B0); + switch(cnt&1) + { + case 0: + return; + //break; + case 1: + v = T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x2B8); + break; + } + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, (u32) sqrt(v)); + T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt & 0x7FFF); + SQRTLOG("BOUT2 sqrt(%08X%08X) = %08X\r\n", (u32)(v>>32), (u32)v, + T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x2B4)); + } + break; + } +} + + +INLINE void MMU_write16_REG_TIMERS(u32 proc, u32 adr, u16 val) { + switch(adr) { + case REG_TM0CNTL : + case REG_TM1CNTL : + case REG_TM2CNTL : + case REG_TM3CNTL : + MMU.timerReload[proc][(adr>>2)&3] = val; + return; + case REG_TM0CNTH : + case REG_TM1CNTH : + case REG_TM2CNTH : + case REG_TM3CNTH : + if(val&0x80) + { + MMU.timer[proc][((adr-2)>>2)&0x3] = MMU.timerReload[proc][((adr-2)>>2)&0x3]; + } + MMU.timerON[proc][((adr-2)>>2)&0x3] = val & 0x80; + switch(val&7) + { + case 0 : + MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 0+1;//proc; + break; + case 1 : + MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 6+1;//proc; + break; + case 2 : + MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 8+1;//proc; + break; + case 3 : + MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 10+1;//proc; + break; + default : + MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 0xFFFF; + break; + } + if(!(val & 0x80)) + MMU.timerRUN[proc][((adr-2)>>2)&0x3] = FALSE; + T1WriteWord(MMU.MMU_MEM[proc][0x40], adr & 0xFFF, val); + return; + } +} + +INLINE void MMU_write16_REG_3D(u32 adr, u16 val) { + switch(adr) { +#ifdef RENDER3D + case 0x04000610 : + LOG("CUT DEPTH %08X\r\n", val); + break; + case 0x04000340 : + OGLRender::glAlphaFunc(val); + break; + case 0x04000354 : + OGLRender::glClearDepth(val); + break; +#endif + } +} + +INLINE void MMU_write32_REG_3D(u32 adr, u32 val) { + switch(adr) { +#ifdef RENDER3D + case 0x04000350 : + OGLRender::glClearColor(val); + return; + case 0x04000400 : + OGLRender::glCallList(val); + return; + case 0x04000440 : + OGLRender::glMatrixMode(val); + return; + case 0x04000444 : + OGLRender::glPushMatrix(); + return; + case 0x04000448 : + OGLRender::glPopMatrix(val); + return; + case 0x0400044C : + OGLRender::glStoreMatrix(val); + return; + case 0x04000450 : + OGLRender::glRestore(); + return; + case 0x04000454 : + OGLRender::glLoadIdentity(); + return; + case 0x04000458 : + OGLRender::ML4x4ajouter(val); + return; + case 0x0400045C : + OGLRender::ML4x3ajouter(val); + return; + case 0x04000460 : + OGLRender::glMultMatrix4x4(val); + return; + case 0x04000464 : + OGLRender::glMultMatrix4x3(val); + return; + case 0x04000468 : + OGLRender::glMultMatrix3x3(val); + return; + case 0x0400046C : + OGLRender::glScale(val); + return; + case 0x04000470 : + OGLRender::addTrans(val); + return; + case 0x04000480 : + OGLRender::glColor3b(val); + return; + case 0x04000488 : + OGLRender::glTexCoord(val); + //execute = FALSE; + return; +#endif + case 0x0400048C : + //OGLRender::glVertex3(val); + return; + case 0x04000490 : + //GPULOG("VERTEX 10 %d\r\n",val); + gl_VTX_10(val); + return; + case 0x04000494 : + //GPULOG(printf(txt, "VERTEXY %d\r\n",val); + gl_VTX_XY(val); + return; + case 0x04000498 : + //GPULOG("VERTEXZ %d\r\n",val); + gl_VTX_XZ(val); + return; + case 0x0400049C : + //GPULOG("VERTEYZ %d\r\n",val); + gl_VTX_YZ(val); + return; + case 0x040004A0 : + gl_VTX_DIFF(val); + return; +#ifdef RENDER3D + case 0x040004A8 : + OGLRender::glTexImage2D(val, FALSE); + //execute = FALSE; + testval = val; + return; + case 0x040004AC : + OGLRender::glTexImage2D(testval, TRUE); + //execute = FALSE; + return; +#endif + case 0x04000500 : + // OGLRender::glBegin(val); + gl_VTX_begin(val); + return; + case 0x04000504 : + // OGLRender::glEnd(); + gl_VTX_end(); + return; +#ifdef RENDER3D + case 0x04000540 : + OGLRender::glFlush(); + return; + case 0x04000580 : + OGLRender::glViewPort(val); + return; +#endif + } +} + + +// FIXME : but the good symbol name here +#ifdef YOUR_ENDIAN_DEFINE +typedef union { + struct { + u8 byte4; u8 byte3; u8 byte2; u8 byte1; + } bytes; + struct { + u16 hword2; u16 hword1; + } hwords; + u32 word; +} u32_union; +#else +typedef union { + struct { + u8 byte1; u8 byte2; u8 byte3; u8 byte4; + } bytes; + struct { + u16 hword1; u16 hword2; + } hwords; + u32 word; +} u32_union; +#endif + +void FASTCALL MMU_writeXX(u32 proc, u32 adr, u32 val, u8 nbbytes) { + u32 adr_u8_1 = adr & 0xFFFFFFFC; + u32 adr_u8_2 = adr_u8_1 + 1; + u32 adr_u8_3 = adr_u8_1 + 2; + u32 adr_u8_4 = adr_u8_1 + 3; +#define MEM_REGION ((adr >> 20)&0xFF) +#define adr_u32 adr_u8_1 +#define adr_u16_1 adr_u8_1 +#define adr_u16_2 adr_u8_3 + u32_union val_union; +#define val_u32 val_union.word +#define val_u16_1 val_union.hwords.hword1 +#define val_u16_2 val_union.hwords.hword2 +#define val_u8_1 val_union.bytes.byte1 +#define val_u8_2 val_union.bytes.byte2 +#define val_u8_3 val_union.bytes.byte3 +#define val_u8_4 val_union.bytes.byte4 + // CFlash writing, Mic - if ((adr>=0x9000000)&&(adr<0x9900000)) { + if ((adr>=0x08800000)&&(adr<0x09900000)) { cflash_write(adr,val); return; } + +#ifdef LOG_CARD + if ((adr>=0x040001A0)&&(adr>=0x040001AF)) { + /* TODO (clear): ??? */ + LOG("%08X : %02X\r\n", adr, val); + return; + } +#endif + + if (proc == ARMCPU_ARM7) { + // This is bad, remove it + if ((adr>=0x04000400)&&(adr<0x0400051D)) + { + SPU_WriteByte(adr, val); + return; + } + + /* wifi mac access */ + if ((adr>=0x04800000)&&(adr<0x05000000)) +#ifdef EXPERIMENTAL_WIFI + if (nbbytes == 2) // u16 data + { + WIFI_write16(&wifiMac,adr,val) ; + return; + } +#else + return; +#endif + } else + + if (/*(proc == ARMCPU_ARM9) &&*/ (adr & ~0x3FFF) == MMU.DTCMRegion) + { + /* Writes data in DTCM (ARM9 only) */ + switch (nbbytes) { + case 1: ARM9Mem.ARM9_DTCM[adr&0x3FFF] = val; break; + case 2: T1WriteWord(ARM9Mem.ARM9_DTCM, adr & 0x3FFF, val); break; + case 4: T1WriteLong(ARM9Mem.ARM9_DTCM, adr & 0x3FFF, val); break; + } + return ; + } adr &= 0x0FFFFFFF; - // This is bad, remove it - if(proc == ARMCPU_ARM7) - { - if ((adr>=0x04000400)&&(adr<0x0400051D)) - { - SPU_WriteByte(adr, val); - return; - } - } - if (adr & 0xFF800000 == 0x04800000) - { - /* is wifi hardware, dont intermix with regular hardware registers */ - /* FIXME handle 8 bit writes */ - return ; + // write data 1st so we can read coherent data + switch (nbbytes) { + case 1: + MMU.MMU_MEM[proc][MEM_REGION][adr&MMU.MMU_MASK[proc][MEM_REGION]]=val; + break; + case 2: + T1WriteWord(MMU.MMU_MEM[proc][MEM_REGION],adr&MMU.MMU_MASK[proc][MEM_REGION],val); + break; + case 4: + T1WriteLong(MMU.MMU_MEM[proc][MEM_REGION],adr&MMU.MMU_MASK[proc][MEM_REGION],val); + break; } + val_union.word = T1ReadLong(MMU.MMU_MEM[proc][MEM_REGION], + adr_u32&MMU.MMU_MASK[proc][MEM_REGION]); + + + // which region + switch (adr & REG_REGION_MASK) { + case REG_BASE_DISPx: + //if (proc == ARMCPU_ARM9) + { + switch (nbbytes) { + case 4: + case 3: + MMU_write16_REG_DISPx(adr_u16_2, val_u16_2); + case 2: + case 1: + MMU_write32_REG_DISPx(adr_u32, val_u32); + MMU_write16_REG_DISPx(adr_u16_1, val_u16_1); + break; + } + } + break; + case REG_BASE_DMA: + MMU_write32_REG_DMA(proc, adr_u32, val_u32); + break; + case REG_BASE_SIORTCTIMERS: + MMU_write16_REG_TIMERS(proc, adr_u16_2, val_u16_2); + MMU_write16_REG_TIMERS(proc, adr_u16_1, val_u16_1); + break; + case REG_BASE_ROMIPC: + switch (nbbytes) { + case 4: + case 3: + MMU_write16_REG_SPI(proc, adr_u16_2, val_u16_2); //SPI + case 2: + case 1: + MMU_write32_REG_ROMIPC(proc, adr_u32, val_u32); //ROM IPC + MMU_write16_REG_SPI(proc, adr_u16_1, val_u16_1); //SPI + break; + } + break; + case REG_BASE_MEMIRQ: + + switch(adr_u32) + { + /* TODO: EEEK ! Controls for VRAMs A, B, C, D are missing ! */ + /* TODO: Not all mappings of VRAMs are handled... (especially BG and OBJ modes) */ + case REG_VRAMCNTA: case REG_VRAMCNTB: + case REG_VRAMCNTC: case REG_VRAMCNTD: + case REG_VRAMCNTE: case REG_VRAMCNTF: + case REG_VRAMCNTG: case REG_VRAMCNTH: + case REG_VRAMCNTI: + if (proc == ARMCPU_ARM9) { + MMU_write8_REG_VRAMCNT(adr_u8_4, val_u8_4); + MMU_write8_REG_VRAMCNT(adr_u8_3, val_u8_3); + MMU_write8_REG_VRAMCNT(adr_u8_2, val_u8_2); + MMU_write8_REG_VRAMCNT(adr_u8_1, val_u8_1); + } + break; + case REG_IME : + MMU.reg_IME[proc] = val_u32 & 1; + break; + case REG_IE: + MMU.reg_IE[proc] = val_u32; + break; + case REG_IF : + MMU.reg_IF[proc] &= (~val_u32); + break; + } + break; + case REG_BASE_MATH: + MMU_write32_REG_MATH(proc, adr_u32, val_u32); + break; + case REG_BASE_RCVPORTS: + break; + case REG_BASE_OTHER: + default: + switch(adr) { + case REG_POWCNT1 : + if(proc == ARMCPU_ARM9) + { + if(val & (1<<15)) { + LOG("Main core on top\n"); + MainScreen.offset = 0; + SubScreen.offset = 192; + //nds.swapScreen(); + } else { + LOG("Main core on bottom (%04X)\n", val); + MainScreen.offset = 192; + SubScreen.offset = 0; + } + } + break; + default : + if(proc == ARMCPU_ARM9) + { + switch (nbbytes) { + case 4: + case 3: + MMU_write16_REG_3D(adr_u16_2, val_u16_2); + case 2: + case 1: + MMU_write16_REG_3D(adr_u16_1, val_u16_1); + MMU_write32_REG_3D(adr_u32, val_u32); + break; + } + + } + break; + } + break; + } +} + + +void FASTCALL MMU_write8_old(u32 proc, u32 adr, u8 val) +{ switch(adr) { @@ -990,89 +2107,89 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) MMU_VRAMReloadFromLCD(adr-REG_VRAMCNTI,val) ; } break; - case REG_DISPA_WIN0H: + case REG_DISPx_WIN0H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(MainScreen.gpu,val,0) ; break ; - case REG_DISPA_WIN0H+1: + case REG_DISPx_WIN0H+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(MainScreen.gpu,val,1) ; break ; - case REG_DISPA_WIN1H: + case REG_DISPx_WIN1H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(MainScreen.gpu,val,2) ; break ; - case REG_DISPA_WIN1H+1: + case REG_DISPx_WIN1H+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(MainScreen.gpu,val,3) ; break ; - case REG_DISPB_WIN0H: + case REG_DISPB | REG_DISPx_WIN0H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(SubScreen.gpu,val,0) ; break ; - case REG_DISPB_WIN0H+1: + case REG_DISPB | REG_DISPx_WIN0H+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(SubScreen.gpu,val,1) ; break ; - case REG_DISPB_WIN1H: + case REG_DISPB | REG_DISPx_WIN1H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(SubScreen.gpu,val,2) ; break ; - case REG_DISPB_WIN1H+1: + case REG_DISPB | REG_DISPx_WIN1H+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM_Component(SubScreen.gpu,val,3) ; break ; - case REG_DISPA_WIN0V: + case REG_DISPx_WIN0V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(MainScreen.gpu,val,0) ; break ; - case REG_DISPA_WIN0V+1: + case REG_DISPx_WIN0V+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(MainScreen.gpu,val,1) ; break ; - case REG_DISPA_WIN1V: + case REG_DISPx_WIN1V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(MainScreen.gpu,val,2) ; break ; - case REG_DISPA_WIN1V+1: + case REG_DISPx_WIN1V+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(MainScreen.gpu,val,3) ; break ; - case REG_DISPB_WIN0V: + case REG_DISPB | REG_DISPx_WIN0V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(SubScreen.gpu,val,0) ; break ; - case REG_DISPB_WIN0V+1: + case REG_DISPB | REG_DISPx_WIN0V+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(SubScreen.gpu,val,1) ; break ; - case REG_DISPB_WIN1V: + case REG_DISPB | REG_DISPx_WIN1V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(SubScreen.gpu,val,2) ; break ; - case REG_DISPB_WIN1V+1: + case REG_DISPB | REG_DISPx_WIN1V+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM_Component(SubScreen.gpu,val,3) ; break ; - case REG_DISPA_WININ: + case REG_DISPx_WININ: if(proc == ARMCPU_ARM9) GPU_setWINDOW_INCNT_Component(MainScreen.gpu,val,0) ; break ; - case REG_DISPA_WININ+1: + case REG_DISPx_WININ+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_INCNT_Component(MainScreen.gpu,val,1) ; break ; - case REG_DISPA_WINOUT: + case REG_DISPx_WINOUT: if(proc == ARMCPU_ARM9) GPU_setWINDOW_OUTCNT_Component(MainScreen.gpu,val,0) ; break ; - case REG_DISPA_WINOUT+1: + case REG_DISPx_WINOUT+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_OUTCNT_Component(MainScreen.gpu,val,1) ; break ; - case REG_DISPB_WININ: + case REG_DISPB | REG_DISPx_WININ: if(proc == ARMCPU_ARM9) GPU_setWINDOW_INCNT_Component(SubScreen.gpu,val,0) ; break ; - case REG_DISPB_WININ+1: + case REG_DISPB | REG_DISPx_WININ+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_INCNT_Component(SubScreen.gpu,val,1) ; break ; - case REG_DISPB_WINOUT: + case REG_DISPB | REG_DISPx_WINOUT: if(proc == ARMCPU_ARM9) GPU_setWINDOW_OUTCNT_Component(SubScreen.gpu,val,0) ; break ; - case REG_DISPB_WINOUT+1: + case REG_DISPB | REG_DISPx_WINOUT+1: if(proc == ARMCPU_ARM9) GPU_setWINDOW_OUTCNT_Component(SubScreen.gpu,val,1) ; break ; - case REG_DISPA_MASTERBRIGHT: - if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (MainScreen.gpu, (val & 0xFF) | (T1ReadWord((u16 *)REG_DISPA_MASTERBRIGHT,0) & 0xFF00)); + case REG_DISPx_MASTERBRIGHT: + if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (MainScreen.gpu, (val & 0xFF) | (T1ReadWord((u16 *)REG_DISPx_MASTERBRIGHT,0) & 0xFF00)); break; - case REG_DISPA_MASTERBRIGHT+1: - if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (MainScreen.gpu, (val & 0xFF00) | (T1ReadWord((u16 *)REG_DISPA_MASTERBRIGHT,0) & 0xFF)); + case REG_DISPx_MASTERBRIGHT+1: + if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (MainScreen.gpu, (val & 0xFF00) | (T1ReadWord((u16 *)REG_DISPx_MASTERBRIGHT,0) & 0xFF)); break; - case REG_DISPB_MASTERBRIGHT: - if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (SubScreen.gpu, (val & 0xFF) | (T1ReadWord((u16 *)REG_DISPB_MASTERBRIGHT,0) & 0xFF00)); + case REG_DISPB | REG_DISPx_MASTERBRIGHT: + if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (SubScreen.gpu, (val & 0xFF) | (T1ReadWord((u16 *)(REG_DISPB | REG_DISPx_MASTERBRIGHT),0) & 0xFF00)); break; - case REG_DISPB_MASTERBRIGHT+1: - if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (SubScreen.gpu, (val & 0xFF00) | (T1ReadWord((u16 *)REG_DISPB_MASTERBRIGHT,0) & 0xFF)); + case REG_DISPB | REG_DISPx_MASTERBRIGHT+1: + if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (SubScreen.gpu, (val & 0xFF00) | (T1ReadWord((u16 *)(REG_DISPB | REG_DISPx_MASTERBRIGHT),0) & 0xFF)); break; #ifdef LOG_CARD @@ -1097,9 +2214,7 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]]=val; } -u16 partie = 1; - -void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) +void FASTCALL MMU_write16_old(u32 proc, u32 adr, u16 val) { if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion)) { @@ -1158,7 +2273,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) OGLRender::glAlphaFunc(val); } return; - case REG_DISPA_DISP3DCNT : + case REG_DISPx_DISP3DCNT : if(proc == ARMCPU_ARM9) { OGLRender::glControl(val); @@ -1315,254 +2430,254 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) /* NOTICE: Perhaps we have to use gbatek-like reg names instead of libnds-like ones ...*/ - case REG_DISPA_BG0HOFS : + case REG_DISPx_BG0HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(MainScreen.gpu, 0, val); return; - case REG_DISPA_BG1HOFS : + case REG_DISPx_BG1HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(MainScreen.gpu, 1, val); return; - case REG_DISPA_BG2HOFS : + case REG_DISPx_BG2HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG3HOFS : + case REG_DISPx_BG3HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG0HOFS : + case REG_DISPB | REG_DISPx_BG0HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(SubScreen.gpu, 0, val); return; - case REG_DISPB_BG1HOFS : + case REG_DISPB | REG_DISPx_BG1HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(SubScreen.gpu, 1, val); return; - case REG_DISPB_BG2HOFS : + case REG_DISPB | REG_DISPx_BG2HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG3HOFS : + case REG_DISPB | REG_DISPx_BG3HOFS : if(proc == ARMCPU_ARM9) GPU_scrollX(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG0VOFS : + case REG_DISPx_BG0VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(MainScreen.gpu, 0, val); return; - case REG_DISPA_BG1VOFS : + case REG_DISPx_BG1VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(MainScreen.gpu, 1, val); return; - case REG_DISPA_BG2VOFS : + case REG_DISPx_BG2VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG3VOFS : + case REG_DISPx_BG3VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG0VOFS : + case REG_DISPB | REG_DISPx_BG0VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(SubScreen.gpu, 0, val); return; - case REG_DISPB_BG1VOFS : + case REG_DISPB | REG_DISPx_BG1VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(SubScreen.gpu, 1, val); return; - case REG_DISPB_BG2VOFS : + case REG_DISPB | REG_DISPx_BG2VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG3VOFS : + case REG_DISPB | REG_DISPx_BG3VOFS : if(proc == ARMCPU_ARM9) GPU_scrollY(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG2PA : + case REG_DISPx_BG2PA : if(proc == ARMCPU_ARM9) GPU_setPA(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2PB : + case REG_DISPx_BG2PB : if(proc == ARMCPU_ARM9) GPU_setPB(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2PC : + case REG_DISPx_BG2PC : if(proc == ARMCPU_ARM9) GPU_setPC(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2PD : + case REG_DISPx_BG2PD : if(proc == ARMCPU_ARM9) GPU_setPD(MainScreen.gpu, 2, val); return; - case REG_DISPB_BG2PA : + case REG_DISPB | REG_DISPx_BG2PA : if(proc == ARMCPU_ARM9) GPU_setPA(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2PB : + case REG_DISPB | REG_DISPx_BG2PB : if(proc == ARMCPU_ARM9) GPU_setPB(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2PC : + case REG_DISPB | REG_DISPx_BG2PC : if(proc == ARMCPU_ARM9) GPU_setPC(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2PD : + case REG_DISPB | REG_DISPx_BG2PD : if(proc == ARMCPU_ARM9) GPU_setPD(SubScreen.gpu, 2, val); return; - case REG_DISPA_BG3PA : + case REG_DISPx_BG3PA : if(proc == ARMCPU_ARM9) GPU_setPA(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3PB : + case REG_DISPx_BG3PB : if(proc == ARMCPU_ARM9) GPU_setPB(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3PC : + case REG_DISPx_BG3PC : if(proc == ARMCPU_ARM9) GPU_setPC(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3PD : + case REG_DISPx_BG3PD : if(proc == ARMCPU_ARM9) GPU_setPD(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG3PA : + case REG_DISPB | REG_DISPx_BG3PA : if(proc == ARMCPU_ARM9) GPU_setPA(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3PB : + case REG_DISPB | REG_DISPx_BG3PB : if(proc == ARMCPU_ARM9) GPU_setPB(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3PC : + case REG_DISPB | REG_DISPx_BG3PC : if(proc == ARMCPU_ARM9) GPU_setPC(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3PD : + case REG_DISPB | REG_DISPx_BG3PD : if(proc == ARMCPU_ARM9) GPU_setPD(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG2XL : + case REG_DISPx_BG2XL : if(proc == ARMCPU_ARM9) GPU_setXL(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2XH : + case REG_DISPx_BG2XH : if(proc == ARMCPU_ARM9) GPU_setXH(MainScreen.gpu, 2, val); return; - case REG_DISPB_BG2XL : + case REG_DISPB | REG_DISPx_BG2XL : if(proc == ARMCPU_ARM9) GPU_setXL(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2XH : + case REG_DISPB | REG_DISPx_BG2XH : if(proc == ARMCPU_ARM9) GPU_setXH(SubScreen.gpu, 2, val); return; - case REG_DISPA_BG3XL : + case REG_DISPx_BG3XL : if(proc == ARMCPU_ARM9) GPU_setXL(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3XH : + case REG_DISPx_BG3XH : if(proc == ARMCPU_ARM9) GPU_setXH(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG3XL : + case REG_DISPB | REG_DISPx_BG3XL : if(proc == ARMCPU_ARM9) GPU_setXL(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3XH : + case REG_DISPB | REG_DISPx_BG3XH : if(proc == ARMCPU_ARM9) GPU_setXH(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG2YL : + case REG_DISPx_BG2YL : if(proc == ARMCPU_ARM9) GPU_setYL(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2YH : + case REG_DISPx_BG2YH : if(proc == ARMCPU_ARM9) GPU_setYH(MainScreen.gpu, 2, val); return; - case REG_DISPB_BG2YL : + case REG_DISPB | REG_DISPx_BG2YL : if(proc == ARMCPU_ARM9) GPU_setYL(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2YH : + case REG_DISPB | REG_DISPx_BG2YH : if(proc == ARMCPU_ARM9) GPU_setYH(SubScreen.gpu, 2, val); return; - case REG_DISPA_BG3YL : + case REG_DISPx_BG3YL : if(proc == ARMCPU_ARM9) GPU_setYL(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3YH : + case REG_DISPx_BG3YH : if(proc == ARMCPU_ARM9) GPU_setYH(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG3YL : + case REG_DISPB | REG_DISPx_BG3YL : if(proc == ARMCPU_ARM9) GPU_setYL(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3YH : + case REG_DISPB | REG_DISPx_BG3YH : if(proc == ARMCPU_ARM9) GPU_setYH(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG0CNT : + case REG_DISPx_BG0CNT : //GPULOG("MAIN BG0 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(MainScreen.gpu, 0, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x8, val); return; - case REG_DISPA_BG1CNT : + case REG_DISPx_BG1CNT : //GPULOG("MAIN BG1 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(MainScreen.gpu, 1, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0xA, val); return; - case REG_DISPA_BG2CNT : + case REG_DISPx_BG2CNT : //GPULOG("MAIN BG2 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(MainScreen.gpu, 2, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0xC, val); return; - case REG_DISPA_BG3CNT : + case REG_DISPx_BG3CNT : //GPULOG("MAIN BG3 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(MainScreen.gpu, 3, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0xE, val); return; - case REG_DISPB_BG0CNT : + case REG_DISPB | REG_DISPx_BG0CNT : //GPULOG("SUB BG0 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(SubScreen.gpu, 0, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x1008, val); return; - case REG_DISPB_BG1CNT : + case REG_DISPB | REG_DISPx_BG1CNT : //GPULOG("SUB BG1 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(SubScreen.gpu, 1, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x100A, val); return; - case REG_DISPB_BG2CNT : + case REG_DISPB | REG_DISPx_BG2CNT : //GPULOG("SUB BG2 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(SubScreen.gpu, 2, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x100C, val); return; - case REG_DISPB_BG3CNT : + case REG_DISPB | REG_DISPx_BG3CNT : //GPULOG("SUB BG3 SETPROP 16B %08X\r\n", val); if(proc == ARMCPU_ARM9) GPU_setBGProp(SubScreen.gpu, 3, val); T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x100E, val); return; - case REG_DISPA_BLDCNT: + case REG_DISPx_BLDCNT: if(proc == ARMCPU_ARM9) GPU_setBLDCNT(MainScreen.gpu,val) ; break ; - case REG_DISPB_BLDCNT: + case REG_DISPB | REG_DISPx_BLDCNT: if(proc == ARMCPU_ARM9) GPU_setBLDCNT(SubScreen.gpu,val) ; break ; - case REG_DISPA_BLDALPHA: + case REG_DISPx_BLDALPHA: if(proc == ARMCPU_ARM9) GPU_setBLDALPHA(MainScreen.gpu,val) ; break ; - case REG_DISPB_BLDALPHA: + case REG_DISPB | REG_DISPx_BLDALPHA: if(proc == ARMCPU_ARM9) GPU_setBLDALPHA(SubScreen.gpu,val) ; break ; - case REG_DISPA_BLDY: + case REG_DISPx_BLDY: if(proc == ARMCPU_ARM9) GPU_setBLDY(MainScreen.gpu,val) ; break ; - case REG_DISPB_BLDY: + case REG_DISPB | REG_DISPx_BLDY: if(proc == ARMCPU_ARM9) GPU_setBLDY(SubScreen.gpu,val) ; break ; - case REG_DISPA_MOSAIC: + case REG_DISPx_MOSAIC: if(proc == ARMCPU_ARM9) GPU_setMOSAIC(MainScreen.gpu,val) ; break ; - case REG_DISPB_MOSAIC: + case REG_DISPB | REG_DISPx_MOSAIC: if(proc == ARMCPU_ARM9) GPU_setMOSAIC(SubScreen.gpu,val) ; break ; - case REG_DISPA_MASTERBRIGHT: + case REG_DISPx_MASTERBRIGHT: if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (MainScreen.gpu, val); break; - case REG_DISPB_MASTERBRIGHT: + case REG_DISPB | REG_DISPx_MASTERBRIGHT: if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (SubScreen.gpu, val); break; - case REG_DISPA_WIN0H: + case REG_DISPx_WIN0H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM(MainScreen.gpu,val,0) ; break ; - case REG_DISPA_WIN1H: + case REG_DISPx_WIN1H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM(MainScreen.gpu,val,1) ; break ; - case REG_DISPB_WIN0H: + case REG_DISPB | REG_DISPx_WIN0H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM(SubScreen.gpu,val,0) ; break ; - case REG_DISPB_WIN1H: + case REG_DISPB | REG_DISPx_WIN1H: if(proc == ARMCPU_ARM9) GPU_setWINDOW_XDIM(SubScreen.gpu,val,1) ; break ; - case REG_DISPA_WIN0V: + case REG_DISPx_WIN0V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM(MainScreen.gpu,val,0) ; break ; - case REG_DISPA_WIN1V: + case REG_DISPx_WIN1V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM(MainScreen.gpu,val,1) ; break ; - case REG_DISPB_WIN0V: + case REG_DISPB | REG_DISPx_WIN0V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM(SubScreen.gpu,val,0) ; break ; - case REG_DISPB_WIN1V: + case REG_DISPB | REG_DISPx_WIN1V: if(proc == ARMCPU_ARM9) GPU_setWINDOW_YDIM(SubScreen.gpu,val,1) ; break ; - case REG_DISPA_WININ: + case REG_DISPx_WININ: if(proc == ARMCPU_ARM9) GPU_setWINDOW_INCNT(MainScreen.gpu, val) ; break ; - case REG_DISPA_WINOUT: + case REG_DISPx_WINOUT: if(proc == ARMCPU_ARM9) GPU_setWINDOW_OUTCNT(MainScreen.gpu, val) ; break ; - case REG_DISPB_WININ: + case REG_DISPB | REG_DISPx_WININ: if(proc == ARMCPU_ARM9) GPU_setWINDOW_INCNT(SubScreen.gpu, val) ; break ; - case REG_DISPB_WINOUT: + case REG_DISPB | REG_DISPx_WINOUT: if(proc == ARMCPU_ARM9) GPU_setWINDOW_OUTCNT(SubScreen.gpu, val) ; break ; case REG_IME : @@ -1677,7 +2792,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) MMU.timerRUN[proc][((adr-2)>>2)&0x3] = FALSE; T1WriteWord(MMU.MMU_MEM[proc][0x40], adr & 0xFFF, val); return; - case REG_DISPA_DISPCNT+2 : + case REG_DISPx_DISPCNT+2 : { //execute = FALSE; u32 v = (T1ReadLong(MMU.MMU_MEM[proc][0x40], 0) & 0xFFFF) | ((u32) val << 16); @@ -1685,7 +2800,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) T1WriteLong(MMU.MMU_MEM[proc][0x40], 0, v); } return; - case REG_DISPA_DISPCNT : + case REG_DISPx_DISPCNT : if(proc == ARMCPU_ARM9) { u32 v = (T1ReadLong(MMU.MMU_MEM[proc][0x40], 0) & 0xFFFF0000) | val; @@ -1699,7 +2814,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) GPU_set_DISPCAPCNT(MainScreen.gpu,val); } return; - case REG_DISPB_DISPCNT+2 : + case REG_DISPB | REG_DISPx_DISPCNT+2 : if(proc == ARMCPU_ARM9) { //execute = FALSE; @@ -1708,7 +2823,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x1000, v); } return; - case REG_DISPB_DISPCNT : + case REG_DISPB | REG_DISPx_DISPCNT : { u32 v = (T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x1000) & 0xFFFF0000) | val; GPU_setVideoProp(SubScreen.gpu, v); @@ -1816,7 +2931,7 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) u32 testval = 0; -void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) +void FASTCALL MMU_write32_old(u32 proc, u32 adr, u32 val) { if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion)) { @@ -2036,109 +3151,109 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) } return; #endif - case REG_DISPA_BG2PA : + case REG_DISPx_BG2PA : if (proc == ARMCPU_ARM9) GPU_setPAPB(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2PC : + case REG_DISPx_BG2PC : if (proc == ARMCPU_ARM9) GPU_setPCPD(MainScreen.gpu, 2, val); return; - case REG_DISPB_BG2PA : + case REG_DISPB | REG_DISPx_BG2PA : if (proc == ARMCPU_ARM9) GPU_setPAPB(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2PC : + case REG_DISPB | REG_DISPx_BG2PC : if (proc == ARMCPU_ARM9) GPU_setPCPD(SubScreen.gpu, 2, val); return; - case REG_DISPA_BG3PA : + case REG_DISPx_BG3PA : if (proc == ARMCPU_ARM9) GPU_setPAPB(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3PC : + case REG_DISPx_BG3PC : if (proc == ARMCPU_ARM9) GPU_setPCPD(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG3PA : + case REG_DISPB | REG_DISPx_BG3PA : if (proc == ARMCPU_ARM9) GPU_setPAPB(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3PC : + case REG_DISPB | REG_DISPx_BG3PC : if (proc == ARMCPU_ARM9) GPU_setPCPD(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG2XL : + case REG_DISPx_BG2XL : if (proc == ARMCPU_ARM9) GPU_setX(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG2YL : + case REG_DISPx_BG2YL : if (proc == ARMCPU_ARM9) GPU_setY(MainScreen.gpu, 2, val); return; - case REG_DISPB_BG2XL : + case REG_DISPB | REG_DISPx_BG2XL : if (proc == ARMCPU_ARM9) GPU_setX(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG2YL : + case REG_DISPB | REG_DISPx_BG2YL : if (proc == ARMCPU_ARM9) GPU_setY(SubScreen.gpu, 2, val); return; - case REG_DISPA_BG3XL : + case REG_DISPx_BG3XL : if (proc == ARMCPU_ARM9) GPU_setX(MainScreen.gpu, 3, val); return; - case REG_DISPA_BG3YL : + case REG_DISPx_BG3YL : if (proc == ARMCPU_ARM9) GPU_setY(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG3XL : + case REG_DISPB | REG_DISPx_BG3XL : if (proc == ARMCPU_ARM9) GPU_setX(SubScreen.gpu, 3, val); return; - case REG_DISPB_BG3YL : + case REG_DISPB | REG_DISPx_BG3YL : if (proc == ARMCPU_ARM9) GPU_setY(SubScreen.gpu, 3, val); return; - case REG_DISPA_BG0HOFS : + case REG_DISPx_BG0HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(MainScreen.gpu, 0, val); return; - case REG_DISPA_BG1HOFS : + case REG_DISPx_BG1HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(MainScreen.gpu, 1, val); return; - case REG_DISPA_BG2HOFS : + case REG_DISPx_BG2HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(MainScreen.gpu, 2, val); return; - case REG_DISPA_BG3HOFS : + case REG_DISPx_BG3HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(MainScreen.gpu, 3, val); return; - case REG_DISPB_BG0HOFS : + case REG_DISPB | REG_DISPx_BG0HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(SubScreen.gpu, 0, val); return; - case REG_DISPB_BG1HOFS : + case REG_DISPB | REG_DISPx_BG1HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(SubScreen.gpu, 1, val); return; - case REG_DISPB_BG2HOFS : + case REG_DISPB | REG_DISPx_BG2HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(SubScreen.gpu, 2, val); return; - case REG_DISPB_BG3HOFS : + case REG_DISPB | REG_DISPx_BG3HOFS : if (proc == ARMCPU_ARM9) GPU_scrollXY(SubScreen.gpu, 3, val); return; - case REG_DISPA_DISPCNT : + case REG_DISPx_DISPCNT : if(proc == ARMCPU_ARM9) GPU_setVideoProp(MainScreen.gpu, val); //GPULOG("MAIN INIT 32B %08X\r\n", val); T1WriteLong(MMU.MMU_MEM[proc][0x40], 0, val); return; - case REG_DISPB_DISPCNT : + case REG_DISPB | REG_DISPx_DISPCNT : if (proc == ARMCPU_ARM9) GPU_setVideoProp(SubScreen.gpu, val); //GPULOG("SUB INIT 32B %08X\r\n", val); T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x1000, val); return; - case REG_DISPA_WININ: + case REG_DISPx_WININ: if(proc == ARMCPU_ARM9) { GPU_setWINDOW_INCNT(MainScreen.gpu, val & 0xFFFF) ; GPU_setWINDOW_OUTCNT(MainScreen.gpu, (val >> 16) & 0xFFFF) ; } break ; - case REG_DISPB_WININ: + case REG_DISPB | REG_DISPx_WININ: if(proc == ARMCPU_ARM9) { GPU_setWINDOW_INCNT(SubScreen.gpu, val & 0xFFFF) ; GPU_setWINDOW_OUTCNT(SubScreen.gpu, (val >> 16) & 0xFFFF) ; } break ; - case REG_DISPA_MASTERBRIGHT: + case REG_DISPx_MASTERBRIGHT: if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (MainScreen.gpu, val & 0xFFFF); break; - case REG_DISPB_MASTERBRIGHT: + case REG_DISPB | REG_DISPx_MASTERBRIGHT: if(proc == ARMCPU_ARM9) GPU_setMASTER_BRIGHT (SubScreen.gpu, val & 0xFFFF); break; case REG_VRAMCNTA: @@ -2526,7 +3641,7 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) } return; - case REG_DISPA_BG0CNT : + case REG_DISPx_BG0CNT : if (proc == ARMCPU_ARM9) { GPU_setBGProp(MainScreen.gpu, 0, (val&0xFFFF)); @@ -2535,7 +3650,7 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) //if((val>>16)==0x400) execute = FALSE; T1WriteLong(ARM9Mem.ARM9_REG, 8, val); return; - case REG_DISPA_BG2CNT : + case REG_DISPx_BG2CNT : if (proc == ARMCPU_ARM9) { GPU_setBGProp(MainScreen.gpu, 2, (val&0xFFFF)); @@ -2543,7 +3658,7 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) } T1WriteLong(ARM9Mem.ARM9_REG, 0xC, val); return; - case REG_DISPB_BG0CNT : + case REG_DISPB | REG_DISPx_BG0CNT : if (proc == ARMCPU_ARM9) { GPU_setBGProp(SubScreen.gpu, 0, (val&0xFFFF)); @@ -2551,7 +3666,7 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) } T1WriteLong(ARM9Mem.ARM9_REG, 0x1008, val); return; - case REG_DISPB_BG2CNT : + case REG_DISPB | REG_DISPx_BG2CNT : if (proc == ARMCPU_ARM9) { GPU_setBGProp(SubScreen.gpu, 2, (val&0xFFFF)); @@ -2559,14 +3674,14 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) } T1WriteLong(ARM9Mem.ARM9_REG, 0x100C, val); return; - case REG_DISPA_BLDCNT: + case REG_DISPx_BLDCNT: if (proc == ARMCPU_ARM9) { GPU_setBLDCNT (MainScreen.gpu,val&0xffff); GPU_setBLDALPHA (MainScreen.gpu,val>>16); } break; - case REG_DISPB_BLDCNT: + case REG_DISPB | REG_DISPx_BLDCNT: if (proc == ARMCPU_ARM9) { GPU_setBLDCNT (SubScreen.gpu,val&0xffff); @@ -2592,6 +3707,27 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) T1WriteLong(MMU.MMU_MEM[proc][(adr>>20)&0xFF], adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF], val); } +#if USE_OLD +void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) { + MMU_write8_old(proc, adr, val); +} +void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) { + MMU_write16_old(proc, adr, val); +} +void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) { + MMU_write32_old(proc, adr, val); +} +#else +void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) { + MMU_writeXX(proc, adr, val,1); +} +void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) { + MMU_writeXX(proc, adr, val, 2); +} +void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) { + MMU_writeXX(proc, adr, val, 4); +} +#endif void FASTCALL MMU_doDMA(u32 proc, u32 num) { diff --git a/desmume/src/gl_vertex.c b/desmume/src/gl_vertex.c index d80da7fea..3d8f14bb4 100755 --- a/desmume/src/gl_vertex.c +++ b/desmume/src/gl_vertex.c @@ -25,38 +25,41 @@ static u16 vx=0,vy=0,vz=0; +//#define print(a) printf a +#define print(a) + INLINE void gl_VTX_one() { float vfx,vfy,vfz; vfx = vx / 4096.; vfy = vy / 4096.; vfz = vz / 4096.; - printf ("\tVTX (x=%.12f,y=%.12f,z=%.12f)\n",vfx,vfy,vfz); + print(("\tVTX (x=%.12f,y=%.12f,z=%.12f)\n",vfx,vfy,vfz)); } void gl_VTX_begin(u32 val) { //see 4000500h - Cmd 40h - BEGIN_VTXS - Start of Vertex List (W) vx=vy=vz=0; - printf ("VTX_begin : "); + print(("VTX_begin : ")); switch(val) { case 0 : // separate triangles (3 vertices for each triangle) - printf ("GL_TRIANGLES\n"); + print(("GL_TRIANGLES\n")); break; case 1 : // separate quads (4 vertices for each triangle) - printf ("GL_QUADS\n"); + print(("GL_QUADS\n")); break; // strips : 1st triangle or quad defined by all vertices // next ones share a segment (so 2 vertices less) case 2 : // triangle strips (1st : 3, next : 1) - printf ("GL_TRIANGLE_STRIP\n"); + print(("GL_TRIANGLE_STRIP\n")); break; case 3 : // quad strips (1st : 4, next : 2) - printf ("GL_QUAD_STRIP\n"); + print(("GL_QUAD_STRIP\n")); break; } } void gl_VTX_end() { //see 4000504h - Cmd 41h - END_VTXS - End of Vertex List (W) - printf ("VTX_end.\n"); + print(("VTX_end.\n")); } diff --git a/desmume/src/registers.h b/desmume/src/registers.h index 952bfa9f9..80f208b89 100644 --- a/desmume/src/registers.h +++ b/desmume/src/registers.h @@ -1,52 +1,66 @@ #ifndef REGISTERS_H #define REGISTERS_H -// Display Engine A -#define REG_DISPA_DISPCNT 0x04000000 +#define REG_REGION_MASK 0x0FFFEF80 +#define REG_BASE_DISPx 0x04000000 +#define REG_BASE_DISPA 0x04000000 +#define REG_BASE_DISPB 0x04001000 +#define REG_BASE_DMA 0x04000080 +#define REG_BASE_SIORTCTIMERS 0x04000100 +#define REG_BASE_ROMIPC 0x04000180 +#define REG_BASE_MEMIRQ 0x04000200 +#define REG_BASE_MATH 0x04000280 +#define REG_BASE_OTHER 0x04000300 +#define REG_BASE_RCVPORTS 0x04100000 + +#define REG_DISPB 0x00001000 +// core A and B specific +#define REG_DISPx_DISPCNT 0x04000000 +#define REG_DISPx_VCOUNT 0x04000006 +#define REG_DISPx_BG0CNT 0x04000008 +#define REG_DISPx_BG1CNT 0x0400000A +#define REG_DISPx_BG2CNT 0x0400000C +#define REG_DISPx_BG3CNT 0x0400000E +#define REG_DISPx_BG0HOFS 0x04000010 +#define REG_DISPx_BG0VOFS 0x04000012 +#define REG_DISPx_BG1HOFS 0x04000014 +#define REG_DISPx_BG1VOFS 0x04000016 +#define REG_DISPx_BG2HOFS 0x04000018 +#define REG_DISPx_BG2VOFS 0x0400001A +#define REG_DISPx_BG3HOFS 0x0400001C +#define REG_DISPx_BG3VOFS 0x0400001E +#define REG_DISPx_BG2PA 0x04000020 +#define REG_DISPx_BG2PB 0x04000022 +#define REG_DISPx_BG2PC 0x04000024 +#define REG_DISPx_BG2PD 0x04000026 +#define REG_DISPx_BG2XL 0x04000028 +#define REG_DISPx_BG2XH 0x0400002A +#define REG_DISPx_BG2YL 0x0400002C +#define REG_DISPx_BG2YH 0x0400002E +#define REG_DISPx_BG3PA 0x04000030 +#define REG_DISPx_BG3PB 0x04000032 +#define REG_DISPx_BG3PC 0x04000034 +#define REG_DISPx_BG3PD 0x04000036 +#define REG_DISPx_BG3XL 0x04000038 +#define REG_DISPx_BG3XH 0x0400003A +#define REG_DISPx_BG3YL 0x0400003C +#define REG_DISPx_BG3YH 0x0400003E +#define REG_DISPx_WIN0H 0x04000040 +#define REG_DISPx_WIN1H 0x04000042 +#define REG_DISPx_WIN0V 0x04000044 +#define REG_DISPx_WIN1V 0x04000046 +#define REG_DISPx_WININ 0x04000048 +#define REG_DISPx_WINOUT 0x0400004A +#define REG_DISPx_MOSAIC 0x0400004C +#define REG_DISPx_BLDCNT 0x04000050 +#define REG_DISPx_BLDALPHA 0x04000052 +#define REG_DISPx_BLDY 0x04000054 +#define REG_DISPx_MASTERBRIGHT 0x0400006C +// core A specific #define REG_DISPA_DISPSTAT 0x04000004 -#define REG_DISPA_VCOUNT 0x04000006 -#define REG_DISPA_BG0CNT 0x04000008 -#define REG_DISPA_BG1CNT 0x0400000A -#define REG_DISPA_BG2CNT 0x0400000C -#define REG_DISPA_BG3CNT 0x0400000E -#define REG_DISPA_BG0HOFS 0x04000010 -#define REG_DISPA_BG0VOFS 0x04000012 -#define REG_DISPA_BG1HOFS 0x04000014 -#define REG_DISPA_BG1VOFS 0x04000016 -#define REG_DISPA_BG2HOFS 0x04000018 -#define REG_DISPA_BG2VOFS 0x0400001A -#define REG_DISPA_BG3HOFS 0x0400001C -#define REG_DISPA_BG3VOFS 0x0400001E -#define REG_DISPA_BG2PA 0x04000020 -#define REG_DISPA_BG2PB 0x04000022 -#define REG_DISPA_BG2PC 0x04000024 -#define REG_DISPA_BG2PD 0x04000026 -#define REG_DISPA_BG2XL 0x04000028 -#define REG_DISPA_BG2XH 0x0400002A -#define REG_DISPA_BG2YL 0x0400002C -#define REG_DISPA_BG2YH 0x0400002E -#define REG_DISPA_BG3PA 0x04000030 -#define REG_DISPA_BG3PB 0x04000032 -#define REG_DISPA_BG3PC 0x04000034 -#define REG_DISPA_BG3PD 0x04000036 -#define REG_DISPA_BG3XL 0x04000038 -#define REG_DISPA_BG3XH 0x0400003A -#define REG_DISPA_BG3YL 0x0400003C -#define REG_DISPA_BG3YH 0x0400003E -#define REG_DISPA_WIN0H 0x04000040 -#define REG_DISPA_WIN1H 0x04000042 -#define REG_DISPA_WIN0V 0x04000044 -#define REG_DISPA_WIN1V 0x04000046 -#define REG_DISPA_WININ 0x04000048 -#define REG_DISPA_WINOUT 0x0400004A -#define REG_DISPA_MOSAIC 0x0400004C -#define REG_DISPA_BLDCNT 0x04000050 -#define REG_DISPA_BLDALPHA 0x04000052 -#define REG_DISPA_BLDY 0x04000054 #define REG_DISPA_DISP3DCNT 0x04000060 #define REG_DISPA_DISPCAPCNT 0x04000064 #define REG_DISPA_DISPMMEMFIFO 0x04000068 -#define REG_DISPA_MASTERBRIGHT 0x0400006C // DMA #define REG_DMA0SAD 0x040000B0 @@ -142,47 +156,6 @@ #define REG_POWCNT2 0x04000304 #define REG_BIOSPROT 0x04000308 -#define REG_DISPB_DISPCNT 0x04001000 -#define REG_DISPB_BG0CNT 0x04001008 -#define REG_DISPB_BG1CNT 0x0400100A -#define REG_DISPB_BG2CNT 0x0400100C -#define REG_DISPB_BG3CNT 0x0400100E -#define REG_DISPB_BG0HOFS 0x04001010 -#define REG_DISPB_BG0VOFS 0x04001012 -#define REG_DISPB_BG1HOFS 0x04001014 -#define REG_DISPB_BG1VOFS 0x04001016 -#define REG_DISPB_BG2HOFS 0x04001018 -#define REG_DISPB_BG2VOFS 0x0400101A -#define REG_DISPB_BG3HOFS 0x0400101C -#define REG_DISPB_BG3VOFS 0x0400101E -#define REG_DISPB_BG2PA 0x04001020 -#define REG_DISPB_BG2PB 0x04001022 -#define REG_DISPB_BG2PC 0x04001024 -#define REG_DISPB_BG2PD 0x04001026 -#define REG_DISPB_BG2XL 0x04001028 -#define REG_DISPB_BG2XH 0x0400102A -#define REG_DISPB_BG2YL 0x0400102C -#define REG_DISPB_BG2YH 0x0400102E -#define REG_DISPB_BG3PA 0x04001030 -#define REG_DISPB_BG3PB 0x04001032 -#define REG_DISPB_BG3PC 0x04001034 -#define REG_DISPB_BG3PD 0x04001036 -#define REG_DISPB_BG3XL 0x04001038 -#define REG_DISPB_BG3XH 0x0400103A -#define REG_DISPB_BG3YL 0x0400103C -#define REG_DISPB_BG3YH 0x0400103E -#define REG_DISPB_WIN0H 0x04001040 -#define REG_DISPB_WIN1H 0x04001042 -#define REG_DISPB_WIN0V 0x04001044 -#define REG_DISPB_WIN1V 0x04001046 -#define REG_DISPB_WININ 0x04001048 -#define REG_DISPB_WINOUT 0x0400104A -#define REG_DISPB_MOSAIC 0x0400104C -#define REG_DISPB_BLDCNT 0x04001050 -#define REG_DISPB_BLDALPHA 0x04001052 -#define REG_DISPB_BLDY 0x04001054 -#define REG_DISPB_MASTERBRIGHT 0x0400106C - // Receive ports #define REG_IPCFIFORECV 0x04100000 #define REG_GCDATAIN 0x04100010 diff --git a/desmume/src/saves.c b/desmume/src/saves.c index a75d07902..f2ebf103e 100644 --- a/desmume/src/saves.c +++ b/desmume/src/saves.c @@ -282,9 +282,9 @@ int savestate_load (const char *file_name) { MMU_write16(ARMCPU_ARM9, 0x04000304, MMU_read16(ARMCPU_ARM9, 0x04000304)); // This should regenerate the graphics configuration - for (i = REG_DISPA_DISPCNT; i<=REG_DISPA_MASTERBRIGHT; i+=2) + for (i = REG_BASE_DISPA; i<=REG_BASE_DISPA + 0x7F; i+=2) MMU_write16(ARMCPU_ARM9, i, MMU_read16(ARMCPU_ARM9, i)); - for (i = REG_DISPB_DISPCNT; i<=REG_DISPB_MASTERBRIGHT; i+=2) + for (i = REG_BASE_DISPB; i<=REG_BASE_DISPB + 0x7F; i+=2) MMU_write16(ARMCPU_ARM9, i, MMU_read16(ARMCPU_ARM9, i)); gzclose (file);