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Removed the proc variables for execdiv and execsqrt since the ARM7 deosn't have the div/sqrt funcs.

This commit is contained in:
luigi__ 2008-12-27 19:19:06 +00:00
parent a99ef67d0a
commit 24e2b77086
1 changed files with 21 additions and 23 deletions
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44
desmume/src/MMU.cpp
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@ -708,25 +708,24 @@ void MMU_unsetRom()
} }
char txt[80]; char txt[80];
template<u32 proc>
void execsqrt() { void execsqrt() {
u32 ret; u32 ret;
u16 cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x2B0); u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0);
switch(cnt&1) switch(cnt&1)
{ {
case 0: { case 0: {
u32 v = T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x2B8); u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
ret = isqrt(v); ret = isqrt(v);
break; break;
} }
case 1: { case 1: {
u64 v = T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x2B8); u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
ret = isqrt(v); ret = isqrt(v);
break; break;
} }
} }
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B4, 0); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2B0, cnt | 0x8000); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, cnt | 0x8000);
MMU.sqrtCycles = (nds.cycles + 26); MMU.sqrtCycles = (nds.cycles + 26);
MMU.sqrtResult = ret; MMU.sqrtResult = ret;
@ -734,27 +733,26 @@ void execsqrt() {
MMU.sqrtRunning = TRUE; MMU.sqrtRunning = TRUE;
} }
template<u32 proc>
void execdiv() { void execdiv() {
u16 cnt = T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x280); u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280);
s64 num,den; s64 num,den;
s64 res,mod; s64 res,mod;
switch(cnt&3) switch(cnt&3)
{ {
case 0: case 0:
num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x290); num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298); den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 36); MMU.divCycles = (nds.cycles + 36);
break; break;
case 3: //gbatek says this is same as mode 1 case 3: //gbatek says this is same as mode 1
case 1: case 1:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290); num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[proc][0x40], 0x298); den = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68); MMU.divCycles = (nds.cycles + 68);
break; break;
case 2: case 2:
num = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x290); num = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
den = (s64) T1ReadQuad(MMU.MMU_MEM[proc][0x40], 0x298); den = (s64) T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298);
MMU.divCycles = (nds.cycles + 68); MMU.divCycles = (nds.cycles + 68);
break; break;
} }
@ -777,11 +775,11 @@ void execdiv() {
(u32)(den>>32), (u32)den, (u32)(den>>32), (u32)den,
(u32)(res>>32), (u32)res); (u32)(res>>32), (u32)res);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A0, 0); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A4, 0); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2A8, 0); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x2AC, 0); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, 0);
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0x280, ((cnt & 0xBFFF) | 0x8000)); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280, ((cnt & 0xBFFF) | 0x8000));
MMU.divResult = res; MMU.divResult = res;
MMU.divMod = mod; MMU.divMod = mod;
@ -2421,26 +2419,26 @@ static void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
case REG_DIVDENOM : case REG_DIVDENOM :
{ {
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298, val); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x298, val);
execdiv<ARMCPU_ARM9>(); execdiv();
return; return;
} }
case REG_DIVDENOM+4 : case REG_DIVDENOM+4 :
{ {
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x29C, val); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x29C, val);
execdiv<ARMCPU_ARM9>(); execdiv();
return; return;
} }
case REG_SQRTPARAM : case REG_SQRTPARAM :
{ {
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8, val); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8, val);
execsqrt<ARMCPU_ARM9>(); execsqrt();
return; return;
} }
case REG_SQRTPARAM+4 : case REG_SQRTPARAM+4 :
{ {
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2BC, val); T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2BC, val);
execsqrt<ARMCPU_ARM9>(); execsqrt();
return; return;
} }
case REG_IPCSYNC : case REG_IPCSYNC :