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367 Commits 1 Branch 122 Tags 59 MiB
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249 Commits

Author SHA1 Message Date
Lior Halphon 67f1566b5e Minor refinement to sweep 2017-09-23 00:23:02 +03:00
Lior Halphon e0a6edac35 Setting sweep period to 0 cancels pending calculate event 2017-09-22 14:53:24 +03:00
Lior Halphon 2ffce49e16 Minor bugfixes related to sweeping 2017-09-22 14:39:39 +03:00
Lior Halphon 75db33559a Current sample index (Channel 1 and 2) is only reset after turning the APU off 2017-09-22 02:25:06 +03:00
Lior Halphon 8f4cd5c412 Corrected behavior for channel 1 and 2 restart 2017-09-22 02:04:29 +03:00
Lior Halphon 882b141478 Fixed dmg_sound-1 2017-09-21 18:32:21 +03:00
Lior Halphon 2ca550273a Fixed dmg_sound-5 2017-09-21 18:18:10 +03:00
Lior Halphon d3c15ef6ca Fixing APU bugs, one at a time: Blargg’s dmg_sound 8.2 2017-09-21 14:52:09 +03:00
Lior Halphon 02ac609f3c Merge branch 'master' into new_apu 2017-09-20 16:16:05 +03:00
Lior Halphon be038dc8e7 Refinement to the last fix 2017-09-20 03:08:54 +03:00
Lior Halphon 57e7782ac4 Interrupt servicing is now more accurate. Fixes mooneye-gb’s ie_push (all models) and Pinball Deluxe (!!!) for CGB mode 2017-09-20 02:49:45 +03:00
Lior Halphon 09b7e2fff4 Fixed a bug in scx_delay’s calculation 2017-09-11 23:56:35 +03:00
Lior Halphon b9bdd6c49c Merge branch 'master' into new_apu 2017-09-10 02:33:40 +03:00
Lior Halphon 14f267b4fa Another whoops 2017-09-09 19:31:05 +03:00
Lior Halphon 02841ddde6 Whoops 2017-09-09 16:55:55 +03:00
Lior Halphon 026baddbab Implemented delayed/future interrupts for DMG hblank interrupt. Restores vblank_stat_intr-GS support. 2017-09-09 13:45:01 +03:00
Lior Halphon 1e90400916 Reimplemented delayed/future interrupts, currently correct only for CGB. 2017-09-09 13:32:12 +03:00
Lior Halphon 742c9e95d3 Updated previous timing improvements to correctly implement double speed behavior 2017-09-08 23:46:38 +03:00
Lior Halphon e5d354e896 Refined SCX’s effects on PPU timing 2017-09-08 23:02:24 +03:00
Lior Halphon 0f1fa3176f Refinements to LCD timing (breaks vblank_stat_intr-GS for now) 2017-09-08 12:59:57 +03:00
Lior Halphon 0f643e01b7 Removing the delayed interrupt mechanism, research is not complete enough for implementation 2017-09-08 12:58:35 +03:00
Lior Halphon ba0e66a5b7 Merge branch 'master' into new_apu 2017-09-04 18:41:13 +03:00
Lior Halphon 72d26c7046 Fixed obscure timer behavior, fixed regression in rapid_toggle.gb. 2017-09-04 18:40:43 +03:00
Lior Halphon 9bde98dede SCY latching is now correctly emulated, rendering mode timing refined. 2017-09-04 15:45:18 +03:00
Lior Halphon a1a13c61bf On CGB, the VBlank and STAT interrupts are “delayed” by one T-cycle (relative to IF) since they’re not aligned to a T-Cycle 2017-09-03 00:41:52 +03:00
Lior Halphon 0532d2a159 A test ROM I wrote seems to contradicts some of AntonioND’s findings regrading PPU timing in CGB mode. CGB mode now behaves like DMG mode until I figure out what caused the difference. 2017-09-02 23:51:02 +03:00
Lior Halphon 9b490396bb Fixed timing when turning the LCD display on during double speed mode 2017-09-02 23:26:45 +03:00
Lior Halphon 54eb51d8db Refined timer interrupt timing 2017-09-02 22:08:20 +03:00
Lior Halphon e7d5cdbb42 Merge branch 'master' into new_apu 2017-08-20 01:37:33 +03:00
Lior Halphon cbbaf2ee84 Refined Window behavior once more, Fixes #12 (While not breaking Donkey Kong or 007) 2017-08-20 01:34:12 +03:00
Lior Halphon 62878fdc7a More accurate div-event handling 2017-08-15 22:27:15 +03:00
Lior Halphon 8d011ca4b9 Accuracy improvements (Sweep) 2017-08-15 22:05:20 +03:00
Lior Halphon d04aaddcbd Added highpass filter 2017-08-15 21:59:11 +03:00
Lior Halphon ca59aca4a6 Fixed a bug where writing to NR52 affected channels 1 and 2’s duty pattern in DMG mode. Fixed NR43 being written to NR44 as well. 2017-08-13 20:26:35 +03:00
Lior Halphon 36943866e2 Better click prevention 2017-08-12 23:35:18 +03:00
Lior Halphon d43daed6a6 Merge branch 'master' into new_apu 2017-08-12 21:43:09 +03:00
Lior Halphon 7df4e56454 KEY1 is only writable in CGB mode; screen should be black is LCD is on while in stop mode. 2017-08-12 21:42:47 +03:00
Lior Halphon dba7370d6d Turns out APU signal is inverted. This fixes Perfect Dark’s audio. 2017-08-12 20:47:55 +03:00
Lior Halphon 688991f57f The volume envelopes and length controls are handled in different phases of the div-divider 2017-08-12 20:17:20 +03:00
Lior Halphon 4b8be255ce Fixed some channel 4 delays, documented a not currently emulated timing quirk. 2017-08-12 19:50:39 +03:00
Lior Halphon 066efab985 In DMG mode, the length registers are not affected by turning the APU on and off. Why? Why not! 2017-08-11 22:23:03 +03:00
Lior Halphon 0e22ad8eb1 Noise channel support 2017-08-11 17:57:08 +03:00
Lior Halphon 1a8bcd314d Accuracy improvements to sweeping (Still not complete though, more research needed) 2017-08-10 19:42:23 +03:00
Lior Halphon ab5611119a Accuracy improvements, especially to the length control 2017-08-02 21:14:23 +03:00
Lior Halphon d65c2247e5 Added channel 1 and 2, fixed accuracy issues with channel 3 2017-07-27 23:11:33 +03:00
Lior Halphon 2936f7fa57 Fixed channel 3 counter behavior, verified with new tests. The DIV register ticks the APU at 512Hz. 2017-07-22 19:51:11 +03:00
Lior Halphon a19ee1e5e0 2MHz audio downscaling support. Implemented NR50 and NR51. 2017-07-21 23:17:48 +03:00
Lior Halphon baccf336d7 Complete rewrite of the APU. Channel 3 is complete and passes all the relevant tests from blargg’s suite, as well as PCM34-based tests. Actual sound output is basic and limited, though. 2017-07-21 19:06:55 +03:00
nattthebear eb7492c6c6 Fix undefined behavior (sequence point modification). GCC 4.6.4 compiles the code incorrectly without this fix. 2017-07-16 21:08:07 -04:00
Lior Halphon c4ccbd5cce Improved serial interrupt timing, fixes boot_sclk_align. 2017-06-23 17:58:04 +03:00