mirror of https://github.com/bsnes-emu/bsnes.git
Update to v074r05 release.
byuu says: Oh good, that turned out to be a lot easier than I expected. Almost all of the work was already done yesterday in porting the SA-1 over to a static map.
This commit is contained in:
Tim Allen
parent
a937f9b79b
commit
ea077a7d96
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@ -38,7 +38,7 @@ void Cartridge::load(Mode cartridge_mode, const lstring &xml_list) {
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has_serial = false;
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parse_xml(xml_list);
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print(xml_list[0], "\n\n");
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//print(xml_list[0], "\n\n");
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if(ram_size > 0) {
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memory::cartram.map(allocate<uint8_t>(ram_size, 0xff), ram_size);
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@ -1,8 +1,5 @@
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#ifdef SA1_CPP
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VBRBus vbrbus;
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SA1Bus sa1bus;
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namespace memory {
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StaticRAM iram(2048);
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//accessed by:
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@ -13,46 +10,6 @@ namespace memory {
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BitmapRAM bitmapram; //SA-1
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}
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//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
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//this is used both to keep VBR-reads from accessing MMIO registers, and
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//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
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//these ports.
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//(* eg, memory::cartram is used directly, as memory::sa1bwram syncs to the S-CPU)
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void VBRBus::init() {
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map(MapMode::Direct, 0x00, 0x3f, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
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map(MapMode::Direct, 0x80, 0xbf, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
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map(MapMode::Direct, 0xc0, 0xff, 0x0000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
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map(MapMode::Linear, 0x00, 0x3f, 0x6000, 0x7fff, { &MappedRAM::read, &memory::cartram }, { &MappedRAM::write, &memory::cartram }, 0, memory::cartram.size());
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map(MapMode::Linear, 0x80, 0xbf, 0x6000, 0x7fff, { &MappedRAM::read, &memory::cartram }, { &MappedRAM::write, &memory::cartram }, 0, memory::cartram.size());
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map(MapMode::Linear, 0x40, 0x4f, 0x0000, 0xffff, { &MappedRAM::read, &memory::cartram }, { &MappedRAM::write, &memory::cartram }, 0, memory::cartram.size());
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map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x07ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
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map(MapMode::Linear, 0x00, 0x3f, 0x3000, 0x37ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
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map(MapMode::Linear, 0x80, 0xbf, 0x0000, 0x07ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
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map(MapMode::Linear, 0x80, 0xbf, 0x3000, 0x37ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
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}
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void SA1Bus::init() {
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map(MapMode::Direct, 0x00, 0x3f, 0x2200, 0x23ff, { &SA1::mmio_read, &sa1 }, { &SA1::mmio_write, &sa1 });
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map(MapMode::Direct, 0x80, 0xbf, 0x2200, 0x23ff, { &SA1::mmio_read, &sa1 }, { &SA1::mmio_write, &sa1 });
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map(MapMode::Direct, 0x00, 0x3f, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
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map(MapMode::Direct, 0x80, 0xbf, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
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map(MapMode::Direct, 0xc0, 0xff, 0x0000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
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map(MapMode::Linear, 0x00, 0x3f, 0x6000, 0x7fff, { &SA1::mmc_sa1_read, &sa1 }, { &SA1::mmc_sa1_write, &sa1 });
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map(MapMode::Linear, 0x80, 0xbf, 0x6000, 0x7fff, { &SA1::mmc_sa1_read, &sa1 }, { &SA1::mmc_sa1_write, &sa1 });
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map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x07ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
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map(MapMode::Linear, 0x00, 0x3f, 0x3000, 0x37ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
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map(MapMode::Linear, 0x80, 0xbf, 0x0000, 0x07ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
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map(MapMode::Linear, 0x80, 0xbf, 0x3000, 0x37ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
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map(MapMode::Linear, 0x40, 0x4f, 0x0000, 0xffff, { &SA1BWRAM::read, &memory::sa1bwram }, { &SA1BWRAM::write, &memory::sa1bwram }, 0, memory::sa1bwram.size());
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map(MapMode::Linear, 0x60, 0x6f, 0x0000, 0xffff, { &BitmapRAM::read, &memory::bitmapram }, { &BitmapRAM::write, &memory::bitmapram }, 0, memory::bitmapram.size());
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}
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//=======
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//SA1IRAM
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//=======
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@ -1,11 +1,3 @@
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struct VBRBus : Bus {
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void init();
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};
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struct SA1Bus : Bus {
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void init();
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};
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struct CPUIRAM : Memory {
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unsigned size() const;
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alwaysinline uint8 read(unsigned);
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@ -17,13 +17,13 @@ void SA1::dma_normal() {
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switch(mmio.sd) {
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case DMA::SourceROM: {
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if((dsa & 0x408000) == 0x008000 || (dsa & 0xc00000) == 0xc00000) {
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data = sa1bus.read(dsa);
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data = bus_read(dsa);
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}
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} break;
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case DMA::SourceBWRAM: {
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if((dsa & 0x40e000) == 0x006000 || (dsa & 0xf00000) == 0x400000) {
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data = sa1bus.read(dsa);
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data = bus_read(dsa);
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}
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} break;
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@ -35,7 +35,7 @@ void SA1::dma_normal() {
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switch(mmio.dd) {
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case DMA::DestBWRAM: {
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if((dda & 0x40e000) == 0x006000 || (dda & 0xf00000) == 0x400000) {
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sa1bus.write(dda, data);
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bus_write(dda, data);
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}
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} break;
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@ -1,5 +1,96 @@
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#ifdef SA1_CPP
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uint8 SA1::bus_read(unsigned addr) {
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if((addr & 0x40fe00) == 0x002200) { //$00-3f|80-bf:2200-23ff
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return mmio_read(addr);
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}
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if((addr & 0x408000) == 0x008000) { //$00-3f|80-bf:8000-ffff
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return mmc_read(addr);
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}
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if((addr & 0xc00000) == 0xc00000) { //$c0-ff:0000-ffff
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return mmc_read(addr);
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}
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if((addr & 0x40e000) == 0x006000) { //$00-3f|80-bf:6000-7fff
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return mmc_sa1_read(addr);
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}
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if((addr & 0x40f800) == 0x000000) { //$00-3f|80-bf:0000-07ff
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return memory::iram.read(addr & 2047);
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}
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if((addr & 0x40f800) == 0x003000) { //$00-3f|80-bf:3000-37ff
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return memory::iram.read(addr & 2047);
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}
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if((addr & 0xf00000) == 0x400000) { //$40-4f:0000-ffff
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return memory::sa1bwram.read(addr & (memory::sa1bwram.size() - 1));
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}
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if((addr & 0xf00000) == 0x600000) { //$60-6f:0000-ffff
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return memory::bitmapram.read(addr & (memory::bitmapram.size() - 1));
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}
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}
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void SA1::bus_write(unsigned addr, uint8 data) {
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if((addr & 0x40fe00) == 0x002200) { //$00-3f|80-bf:2200-23ff
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return mmio_write(addr, data);
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}
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if((addr & 0x40e000) == 0x006000) { //$00-3f|80-bf:6000-7fff
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return mmc_sa1_write(addr, data);
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}
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if((addr & 0x40f800) == 0x000000) { //$00-3f|80-bf:0000-07ff
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return memory::iram.write(addr & 2047, data);
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}
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if((addr & 0x40f800) == 0x003000) { //$00-3f|80-bf:3000-37ff
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return memory::iram.write(addr & 2047, data);
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}
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if((addr & 0xf00000) == 0x400000) { //$40-4f:0000-ffff
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return memory::sa1bwram.write(addr & (memory::sa1bwram.size() - 1), data);
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}
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if((addr & 0xf00000) == 0x600000) { //$60-6f:0000-ffff
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return memory::bitmapram.write(addr & (memory::bitmapram.size() - 1), data);
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}
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}
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//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
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//this is used both to keep VBR-reads from accessing MMIO registers, and
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//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
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//these ports.
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//(* eg, memory::cartram is used directly, as memory::sa1bwram syncs to the S-CPU)
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uint8 SA1::vbr_read(unsigned addr) {
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if((addr & 0x408000) == 0x008000) { //$00-3f|80-bf:8000-ffff
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return mmc_read(addr);
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}
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if((addr & 0xc00000) == 0xc00000) { //$c0-ff:0000-ffff
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return mmc_read(addr);
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}
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if((addr & 0x40e000) == 0x006000) { //$00-3f|80-bf:6000-7fff
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return memory::cartram.read(addr & (memory::cartram.size() - 1));
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}
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if((addr & 0xf00000) == 0x400000) { //$40-4f:0000-ffff
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return memory::cartram.read(addr & (memory::cartram.size() - 1));
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}
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if((addr & 0x40f800) == 0x000000) { //$00-3f|80-bf:0000-07ff
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return memory::iram.read(addr & 2047);
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}
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if((addr & 0x40f800) == 0x003000) { //$00-3f|80-bf:3000-37ff
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return memory::iram.read(addr & 0x2047);
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}
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}
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//ROM, I-RAM and MMIO registers are accessed at ~10.74MHz (2 clock ticks)
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//BW-RAM is accessed at ~5.37MHz (4 clock ticks)
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//tick() == 2 clock ticks
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@ -12,13 +103,13 @@ void SA1::op_io() {
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uint8 SA1::op_read(unsigned addr) {
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tick();
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if(((addr & 0x40e000) == 0x006000) || ((addr & 0xd00000) == 0x400000)) tick();
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return sa1bus.read(addr);
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return bus_read(addr);
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}
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void SA1::op_write(unsigned addr, uint8 data) {
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tick();
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if(((addr & 0x40e000) == 0x006000) || ((addr & 0xd00000) == 0x400000)) tick();
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sa1bus.write(addr, data);
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bus_write(addr, data);
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}
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uint8 SA1::mmc_read(unsigned addr) {
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@ -1,3 +1,7 @@
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uint8 bus_read(unsigned addr);
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void bus_write(unsigned addr, uint8 data);
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uint8 vbr_read(unsigned addr);
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alwaysinline void op_io();
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alwaysinline uint8 op_read(unsigned addr);
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alwaysinline void op_write(unsigned addr, uint8 data);
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@ -414,18 +414,18 @@ uint8 SA1::mmio_r230b() { return mmio.overflow << 7; }
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//(VDPL) variable-length data read port low
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uint8 SA1::mmio_r230c() {
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uint32 data = (vbrbus.read(mmio.va + 0) << 0)
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| (vbrbus.read(mmio.va + 1) << 8)
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| (vbrbus.read(mmio.va + 2) << 16);
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uint32 data = (vbr_read(mmio.va + 0) << 0)
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| (vbr_read(mmio.va + 1) << 8)
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| (vbr_read(mmio.va + 2) << 16);
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data >>= mmio.vbit;
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return data >> 0;
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}
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//(VDPH) variable-length data read port high
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uint8 SA1::mmio_r230d() {
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uint32 data = (vbrbus.read(mmio.va + 0) << 0)
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| (vbrbus.read(mmio.va + 1) << 8)
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| (vbrbus.read(mmio.va + 2) << 16);
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uint32 data = (vbr_read(mmio.va + 0) << 0)
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| (vbr_read(mmio.va + 1) << 8)
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| (vbr_read(mmio.va + 2) << 16);
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data >>= mmio.vbit;
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if(mmio.hl == 1) {
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@ -129,8 +129,6 @@ void SA1::power() {
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void SA1::reset() {
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create(SA1::Enter, system.cpu_frequency());
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vbrbus.init();
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sa1bus.init();
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memory::cc1bwram.dma = false;
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for(unsigned addr = 0; addr < memory::iram.size(); addr++) {
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@ -36,4 +36,3 @@ public:
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};
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extern SA1 sa1;
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extern SA1Bus sa1bus;
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@ -1,7 +1,7 @@
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namespace SNES {
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namespace Info {
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static const char Name[] = "bsnes";
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static const char Version[] = "074.04";
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static const char Version[] = "074.05";
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static const unsigned SerializerVersion = 17;
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}
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}
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