diff --git a/bsnes/snes/cartridge/cartridge.cpp b/bsnes/snes/cartridge/cartridge.cpp
index b054afd5..c33375e5 100755
--- a/bsnes/snes/cartridge/cartridge.cpp
+++ b/bsnes/snes/cartridge/cartridge.cpp
@@ -38,7 +38,7 @@ void Cartridge::load(Mode cartridge_mode, const lstring &xml_list) {
   has_serial     = false;
 
   parse_xml(xml_list);
-  print(xml_list[0], "\n\n");
+//print(xml_list[0], "\n\n");
 
   if(ram_size > 0) {
     memory::cartram.map(allocate<uint8_t>(ram_size, 0xff), ram_size);
diff --git a/bsnes/snes/chip/sa1/bus/bus.cpp b/bsnes/snes/chip/sa1/bus/bus.cpp
index 11cd52d5..6b05c89a 100755
--- a/bsnes/snes/chip/sa1/bus/bus.cpp
+++ b/bsnes/snes/chip/sa1/bus/bus.cpp
@@ -1,8 +1,5 @@
 #ifdef SA1_CPP
 
-VBRBus vbrbus;
-SA1Bus sa1bus;
-
 namespace memory {
   StaticRAM iram(2048);
                         //accessed by:
@@ -13,46 +10,6 @@ namespace memory {
   BitmapRAM bitmapram;  //SA-1
 }
 
-//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
-//this is used both to keep VBR-reads from accessing MMIO registers, and
-//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
-//these ports.
-//(* eg, memory::cartram is used directly, as memory::sa1bwram syncs to the S-CPU)
-void VBRBus::init() {
-  map(MapMode::Direct, 0x00, 0x3f, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
-  map(MapMode::Direct, 0x80, 0xbf, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
-  map(MapMode::Direct, 0xc0, 0xff, 0x0000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
-
-  map(MapMode::Linear, 0x00, 0x3f, 0x6000, 0x7fff, { &MappedRAM::read, &memory::cartram }, { &MappedRAM::write, &memory::cartram }, 0, memory::cartram.size());
-  map(MapMode::Linear, 0x80, 0xbf, 0x6000, 0x7fff, { &MappedRAM::read, &memory::cartram }, { &MappedRAM::write, &memory::cartram }, 0, memory::cartram.size());
-  map(MapMode::Linear, 0x40, 0x4f, 0x0000, 0xffff, { &MappedRAM::read, &memory::cartram }, { &MappedRAM::write, &memory::cartram }, 0, memory::cartram.size());
-
-  map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x07ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
-  map(MapMode::Linear, 0x00, 0x3f, 0x3000, 0x37ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
-  map(MapMode::Linear, 0x80, 0xbf, 0x0000, 0x07ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
-  map(MapMode::Linear, 0x80, 0xbf, 0x3000, 0x37ff, { &StaticRAM::read, &memory::iram }, { &StaticRAM::write, &memory::iram }, 0, 2048);
-}
-
-void SA1Bus::init() {
-  map(MapMode::Direct, 0x00, 0x3f, 0x2200, 0x23ff, { &SA1::mmio_read, &sa1 }, { &SA1::mmio_write, &sa1 });
-  map(MapMode::Direct, 0x80, 0xbf, 0x2200, 0x23ff, { &SA1::mmio_read, &sa1 }, { &SA1::mmio_write, &sa1 });
-
-  map(MapMode::Direct, 0x00, 0x3f, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
-  map(MapMode::Direct, 0x80, 0xbf, 0x8000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
-  map(MapMode::Direct, 0xc0, 0xff, 0x0000, 0xffff, { &SA1::mmc_read, &sa1 }, { &SA1::mmc_write, &sa1 });
-
-  map(MapMode::Linear, 0x00, 0x3f, 0x6000, 0x7fff, { &SA1::mmc_sa1_read, &sa1 }, { &SA1::mmc_sa1_write, &sa1 });
-  map(MapMode::Linear, 0x80, 0xbf, 0x6000, 0x7fff, { &SA1::mmc_sa1_read, &sa1 }, { &SA1::mmc_sa1_write, &sa1 });
-
-  map(MapMode::Linear, 0x00, 0x3f, 0x0000, 0x07ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
-  map(MapMode::Linear, 0x00, 0x3f, 0x3000, 0x37ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
-  map(MapMode::Linear, 0x80, 0xbf, 0x0000, 0x07ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
-  map(MapMode::Linear, 0x80, 0xbf, 0x3000, 0x37ff, { &SA1IRAM::read, &memory::sa1iram }, { &SA1IRAM::write, &memory::sa1iram }, 0, 2048);
-
-  map(MapMode::Linear, 0x40, 0x4f, 0x0000, 0xffff, { &SA1BWRAM::read, &memory::sa1bwram }, { &SA1BWRAM::write, &memory::sa1bwram }, 0, memory::sa1bwram.size());
-  map(MapMode::Linear, 0x60, 0x6f, 0x0000, 0xffff, { &BitmapRAM::read, &memory::bitmapram }, { &BitmapRAM::write, &memory::bitmapram }, 0, memory::bitmapram.size());
-}
-
 //=======
 //SA1IRAM
 //=======
diff --git a/bsnes/snes/chip/sa1/bus/bus.hpp b/bsnes/snes/chip/sa1/bus/bus.hpp
index 0414c98b..7b94ce76 100755
--- a/bsnes/snes/chip/sa1/bus/bus.hpp
+++ b/bsnes/snes/chip/sa1/bus/bus.hpp
@@ -1,11 +1,3 @@
-struct VBRBus : Bus {
-  void init();
-};
-
-struct SA1Bus : Bus {
-  void init();
-};
-
 struct CPUIRAM : Memory {
   unsigned size() const;
   alwaysinline uint8 read(unsigned);
diff --git a/bsnes/snes/chip/sa1/dma/dma.cpp b/bsnes/snes/chip/sa1/dma/dma.cpp
index aecb7358..8c8f6cb6 100755
--- a/bsnes/snes/chip/sa1/dma/dma.cpp
+++ b/bsnes/snes/chip/sa1/dma/dma.cpp
@@ -17,13 +17,13 @@ void SA1::dma_normal() {
     switch(mmio.sd) {
       case DMA::SourceROM: {
         if((dsa & 0x408000) == 0x008000 || (dsa & 0xc00000) == 0xc00000) {
-          data = sa1bus.read(dsa);
+          data = bus_read(dsa);
         }
       } break;
 
       case DMA::SourceBWRAM: {
         if((dsa & 0x40e000) == 0x006000 || (dsa & 0xf00000) == 0x400000) {
-          data = sa1bus.read(dsa);
+          data = bus_read(dsa);
         }
       } break;
 
@@ -35,7 +35,7 @@ void SA1::dma_normal() {
     switch(mmio.dd) {
       case DMA::DestBWRAM: {
         if((dda & 0x40e000) == 0x006000 || (dda & 0xf00000) == 0x400000) {
-          sa1bus.write(dda, data);
+          bus_write(dda, data);
         }
       } break;
 
diff --git a/bsnes/snes/chip/sa1/memory/memory.cpp b/bsnes/snes/chip/sa1/memory/memory.cpp
index 691094b2..5c6793ca 100755
--- a/bsnes/snes/chip/sa1/memory/memory.cpp
+++ b/bsnes/snes/chip/sa1/memory/memory.cpp
@@ -1,5 +1,96 @@
 #ifdef SA1_CPP
 
+uint8 SA1::bus_read(unsigned addr) {
+  if((addr & 0x40fe00) == 0x002200) {  //$00-3f|80-bf:2200-23ff
+    return mmio_read(addr);
+  }
+
+  if((addr & 0x408000) == 0x008000) {  //$00-3f|80-bf:8000-ffff
+    return mmc_read(addr);
+  }
+
+  if((addr & 0xc00000) == 0xc00000) {  //$c0-ff:0000-ffff
+    return mmc_read(addr);
+  }
+
+  if((addr & 0x40e000) == 0x006000) {  //$00-3f|80-bf:6000-7fff
+    return mmc_sa1_read(addr);
+  }
+
+  if((addr & 0x40f800) == 0x000000) {  //$00-3f|80-bf:0000-07ff
+    return memory::iram.read(addr & 2047);
+  }
+
+  if((addr & 0x40f800) == 0x003000) {  //$00-3f|80-bf:3000-37ff
+    return memory::iram.read(addr & 2047);
+  }
+
+  if((addr & 0xf00000) == 0x400000) {  //$40-4f:0000-ffff
+    return memory::sa1bwram.read(addr & (memory::sa1bwram.size() - 1));
+  }
+
+  if((addr & 0xf00000) == 0x600000) {  //$60-6f:0000-ffff
+    return memory::bitmapram.read(addr & (memory::bitmapram.size() - 1));
+  }
+}
+
+void SA1::bus_write(unsigned addr, uint8 data) {
+  if((addr & 0x40fe00) == 0x002200) {  //$00-3f|80-bf:2200-23ff
+    return mmio_write(addr, data);
+  }
+
+  if((addr & 0x40e000) == 0x006000) {  //$00-3f|80-bf:6000-7fff
+    return mmc_sa1_write(addr, data);
+  }
+
+  if((addr & 0x40f800) == 0x000000) {  //$00-3f|80-bf:0000-07ff
+    return memory::iram.write(addr & 2047, data);
+  }
+
+  if((addr & 0x40f800) == 0x003000) {  //$00-3f|80-bf:3000-37ff
+    return memory::iram.write(addr & 2047, data);
+  }
+
+  if((addr & 0xf00000) == 0x400000) {  //$40-4f:0000-ffff
+    return memory::sa1bwram.write(addr & (memory::sa1bwram.size() - 1), data);
+  }
+
+  if((addr & 0xf00000) == 0x600000) {  //$60-6f:0000-ffff
+    return memory::bitmapram.write(addr & (memory::bitmapram.size() - 1), data);
+  }
+}
+
+//$230c (VDPL), $230d (VDPH) use this bus to read variable-length data.
+//this is used both to keep VBR-reads from accessing MMIO registers, and
+//to avoid syncing the S-CPU and SA-1*; as both chips are able to access
+//these ports.
+//(* eg, memory::cartram is used directly, as memory::sa1bwram syncs to the S-CPU)
+uint8 SA1::vbr_read(unsigned addr) {
+  if((addr & 0x408000) == 0x008000) {  //$00-3f|80-bf:8000-ffff
+    return mmc_read(addr);
+  }
+
+  if((addr & 0xc00000) == 0xc00000) {  //$c0-ff:0000-ffff
+    return mmc_read(addr);
+  }
+
+  if((addr & 0x40e000) == 0x006000) {  //$00-3f|80-bf:6000-7fff
+    return memory::cartram.read(addr & (memory::cartram.size() - 1));
+  }
+
+  if((addr & 0xf00000) == 0x400000) {  //$40-4f:0000-ffff
+    return memory::cartram.read(addr & (memory::cartram.size() - 1));
+  }
+
+  if((addr & 0x40f800) == 0x000000) {  //$00-3f|80-bf:0000-07ff
+    return memory::iram.read(addr & 2047);
+  }
+
+  if((addr & 0x40f800) == 0x003000) {  //$00-3f|80-bf:3000-37ff
+    return memory::iram.read(addr & 0x2047);
+  }
+}
+
 //ROM, I-RAM and MMIO registers are accessed at ~10.74MHz (2 clock ticks)
 //BW-RAM is accessed at ~5.37MHz (4 clock ticks)
 //tick() == 2 clock ticks
@@ -12,13 +103,13 @@ void SA1::op_io() {
 uint8 SA1::op_read(unsigned addr) {
   tick();
   if(((addr & 0x40e000) == 0x006000) || ((addr & 0xd00000) == 0x400000)) tick();
-  return sa1bus.read(addr);
+  return bus_read(addr);
 }
 
 void SA1::op_write(unsigned addr, uint8 data) {
   tick();
   if(((addr & 0x40e000) == 0x006000) || ((addr & 0xd00000) == 0x400000)) tick();
-  sa1bus.write(addr, data);
+  bus_write(addr, data);
 }
 
 uint8 SA1::mmc_read(unsigned addr) {
diff --git a/bsnes/snes/chip/sa1/memory/memory.hpp b/bsnes/snes/chip/sa1/memory/memory.hpp
index abda84fe..51d50ea4 100755
--- a/bsnes/snes/chip/sa1/memory/memory.hpp
+++ b/bsnes/snes/chip/sa1/memory/memory.hpp
@@ -1,3 +1,7 @@
+uint8 bus_read(unsigned addr);
+void bus_write(unsigned addr, uint8 data);
+uint8 vbr_read(unsigned addr);
+
 alwaysinline void op_io();
 alwaysinline uint8 op_read(unsigned addr);
 alwaysinline void op_write(unsigned addr, uint8 data);
diff --git a/bsnes/snes/chip/sa1/mmio/mmio.cpp b/bsnes/snes/chip/sa1/mmio/mmio.cpp
index 12edfc01..b88eae82 100755
--- a/bsnes/snes/chip/sa1/mmio/mmio.cpp
+++ b/bsnes/snes/chip/sa1/mmio/mmio.cpp
@@ -414,18 +414,18 @@ uint8 SA1::mmio_r230b() { return mmio.overflow << 7; }
 
 //(VDPL) variable-length data read port low
 uint8 SA1::mmio_r230c() {
-  uint32 data = (vbrbus.read(mmio.va + 0) <<  0)
-              | (vbrbus.read(mmio.va + 1) <<  8)
-              | (vbrbus.read(mmio.va + 2) << 16);
+  uint32 data = (vbr_read(mmio.va + 0) <<  0)
+              | (vbr_read(mmio.va + 1) <<  8)
+              | (vbr_read(mmio.va + 2) << 16);
   data >>= mmio.vbit;
   return data >> 0;
 }
 
 //(VDPH) variable-length data read port high
 uint8 SA1::mmio_r230d() {
-  uint32 data = (vbrbus.read(mmio.va + 0) <<  0)
-              | (vbrbus.read(mmio.va + 1) <<  8)
-              | (vbrbus.read(mmio.va + 2) << 16);
+  uint32 data = (vbr_read(mmio.va + 0) <<  0)
+              | (vbr_read(mmio.va + 1) <<  8)
+              | (vbr_read(mmio.va + 2) << 16);
   data >>= mmio.vbit;
 
   if(mmio.hl == 1) {
diff --git a/bsnes/snes/chip/sa1/sa1.cpp b/bsnes/snes/chip/sa1/sa1.cpp
index 376f3861..b34dc5ec 100755
--- a/bsnes/snes/chip/sa1/sa1.cpp
+++ b/bsnes/snes/chip/sa1/sa1.cpp
@@ -129,8 +129,6 @@ void SA1::power() {
 
 void SA1::reset() {
   create(SA1::Enter, system.cpu_frequency());
-  vbrbus.init();
-  sa1bus.init();
 
   memory::cc1bwram.dma = false;
   for(unsigned addr = 0; addr < memory::iram.size(); addr++) {
diff --git a/bsnes/snes/chip/sa1/sa1.hpp b/bsnes/snes/chip/sa1/sa1.hpp
index 83b3f4ff..2ea04567 100755
--- a/bsnes/snes/chip/sa1/sa1.hpp
+++ b/bsnes/snes/chip/sa1/sa1.hpp
@@ -36,4 +36,3 @@ public:
 };
 
 extern SA1 sa1;
-extern SA1Bus sa1bus;
diff --git a/bsnes/snes/snes.hpp b/bsnes/snes/snes.hpp
index 55a6a2fa..e79311ca 100755
--- a/bsnes/snes/snes.hpp
+++ b/bsnes/snes/snes.hpp
@@ -1,7 +1,7 @@
 namespace SNES {
   namespace Info {
     static const char Name[] = "bsnes";
-    static const char Version[] = "074.04";
+    static const char Version[] = "074.05";
     static const unsigned SerializerVersion = 17;
   }
 }