Update to v095r05 release.
byuu says:
Changelog:
- GBA: lots of emulation improvements
- PPU PRAM is 16-bits wide
- DMA masks &~1/Half, &~3/Word
- VRAM OBJ 8-bit writes are ignored
- OAM 8-bit writes are ignored
- BGnCNT unused bits are writable*
- BG(0,1)CNT can't set the d13
- BLDALPHA is readable (fixes Donkey Kong Country, etc)
- SNES: lots of code cleanups
- sfc/chip => sfc/coprocessor
- UI: save most recent controller selection
GBA test scores: 1552/1552, 37/38, 1020/1260
(* forgot to add the value to the read function, so endrift's I/O tests
for them will fail. Fixed locally.)
Note: SNES is the only system with multiple controller/expansion port
options, and as such is the only one with a "None" option. Because it's
shared by the controller and expansion port, it ends up sorted first in
the list. This means that on your first run, you'll need to go to Super
Famicom->Controller Port 1 and select "Gamepad", otherwise input won't
work.
Also note that changing the expansion port device requires loading a new
cart. Unlike controllers, you aren't meant to hotplug expansion port
devices.
2015-11-12 10:15:03 +00:00
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auto CPU::portRead(uint2 port) const -> uint8 {
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return status.port[port];
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}
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2010-08-09 13:28:56 +00:00
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Update to v095r05 release.
byuu says:
Changelog:
- GBA: lots of emulation improvements
- PPU PRAM is 16-bits wide
- DMA masks &~1/Half, &~3/Word
- VRAM OBJ 8-bit writes are ignored
- OAM 8-bit writes are ignored
- BGnCNT unused bits are writable*
- BG(0,1)CNT can't set the d13
- BLDALPHA is readable (fixes Donkey Kong Country, etc)
- SNES: lots of code cleanups
- sfc/chip => sfc/coprocessor
- UI: save most recent controller selection
GBA test scores: 1552/1552, 37/38, 1020/1260
(* forgot to add the value to the read function, so endrift's I/O tests
for them will fail. Fixed locally.)
Note: SNES is the only system with multiple controller/expansion port
options, and as such is the only one with a "None" option. Because it's
shared by the controller and expansion port, it ends up sorted first in
the list. This means that on your first run, you'll need to go to Super
Famicom->Controller Port 1 and select "Gamepad", otherwise input won't
work.
Also note that changing the expansion port device requires loading a new
cart. Unlike controllers, you aren't meant to hotplug expansion port
devices.
2015-11-12 10:15:03 +00:00
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auto CPU::portWrite(uint2 port, uint8 data) -> void {
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status.port[port] = data;
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}
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Updated to v067r23 release.
byuu says:
Added missing $4200 IRQ lock, which fixes Chou Aniki on the fast CPU
core, so slower PCs can get their brotherly love on.
Added range-based controller IOBit latching to the fast CPU core, which
enables Super Scope and Justifier support. Uses the priority queue as
well, so there is zero speed-hit. Given the way range-testing works, the
trigger point may vary by 1-2 pixels when firing at the same spot. Not
really a big deal when it avoids a massive speed penalty.
Fixed PAL and interlace-mode HVIRQs at V=0,H<2 on the fast CPU core.
Added the dot-renderer's sprite list update-on-OAM-write functionality
to the scanline-based PPU renderer. Unfortunately it looks like all the
speed gain was already taken from the global dirty flag I was using
before, but this certainly won't hurt speed any, so whatever.
Added #ifdef to stop CoInitialize(0) on non-Windows ports.
Added #ifdefs to stop gradient fade on Windows port. Not going to fuck
over the Linux port aesthetic because of Qt bug #47,326,927. If there's
a way to tell what Qt theme is being used, I can leave it enabled for
XP/Vista themes.
Moved HDMA trigger from 1104 to 1112, and reduced channel overhead from
24 to 16, to better simulate one-cycle DMA->CPU sync.
Code clarity: I've re-added my varint.hpp classes, and am actively using
them in the accuracy cores. So far, I haven't done anything that would
detriment speed, but it is certainly cool. The APU ports exposed by the
CPU and SMP now take uint2 address arguments, the CPU WRAM address
register is a uint17, and the IRQ H/VTIME values are uint10. This
basically allows the source to clearly convey the data sizes, and
eliminates the need to manually mask values when writing to registers or
reading from memory. I'm going to be doing this everywhere, and it will
have a speed impact eventually, because the automation means we can't
skip masks when we know the data is already masked off.
Source: archive contains the launcher code, so that I can look into why
it's crashing on XP tomorrow.
It doesn't look like Circuit USA's flags are going to work too well with
this new CPU core. Still not sure what the hell Robocop vs The
Terminator is doing, I'll read through the mega SNES thread for clues
tomorrow. Speedy Gonzales is definitely broken, as modifying the MDR was
breaking things with my current core. Probably because the new CPU core
doesn't wait for a cycle edge to trigger.
I was thinking that perhaps we could keep some form of cheat codes list
to work as game-specific hacks for the performance core. Keeps the hacks
out of the emulator, but could allow the remaining bugs to be worked
around for people who have no choice but to use the performance core.
2010-08-16 09:42:20 +00:00
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2016-03-26 01:56:15 +00:00
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auto CPU::io() -> void {
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2010-08-09 13:28:56 +00:00
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status.clock_count = 6;
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2016-03-26 01:56:15 +00:00
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dmaEdge();
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addClocks(6);
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aluEdge();
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2010-08-09 13:28:56 +00:00
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}
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2016-03-26 01:56:15 +00:00
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auto CPU::read(uint24 addr) -> uint8 {
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2010-08-09 13:28:56 +00:00
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status.clock_count = speed(addr);
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2016-03-26 01:56:15 +00:00
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dmaEdge();
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addClocks(status.clock_count - 4);
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2015-12-14 09:41:06 +00:00
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regs.mdr = bus.read(addr, regs.mdr);
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2016-03-26 01:56:15 +00:00
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addClocks(4);
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aluEdge();
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2014-02-02 21:02:18 +00:00
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debugger.op_read(addr, regs.mdr);
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2010-08-09 13:28:56 +00:00
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return regs.mdr;
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}
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2016-03-26 01:56:15 +00:00
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auto CPU::write(uint24 addr, uint8 data) -> void {
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aluEdge();
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2010-08-09 13:28:56 +00:00
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status.clock_count = speed(addr);
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2016-03-26 01:56:15 +00:00
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dmaEdge();
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addClocks(status.clock_count);
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2010-08-09 13:28:56 +00:00
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bus.write(addr, regs.mdr = data);
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2014-02-02 21:02:18 +00:00
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debugger.op_write(addr, regs.mdr);
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2010-08-09 13:28:56 +00:00
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}
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2016-02-16 09:32:49 +00:00
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auto CPU::speed(uint24 addr) const -> uint {
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2010-08-09 13:28:56 +00:00
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if(addr & 0x408000) {
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if(addr & 0x800000) return status.rom_speed;
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return 8;
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}
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if((addr + 0x6000) & 0x4000) return 8;
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if((addr - 0x4000) & 0x7e00) return 6;
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return 12;
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}
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2016-03-26 01:56:15 +00:00
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auto CPU::disassemblerRead(uint24 addr) -> uint8 {
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2015-12-14 09:41:06 +00:00
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return bus.read(addr, regs.mdr);
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2012-04-29 06:16:44 +00:00
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}
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