bsnes/higan/sfc/cpu/memory/memory.cpp

49 lines
1.0 KiB
C++
Raw Normal View History

auto CPU::portRead(uint2 port) const -> uint8 {
return status.port[port];
}
auto CPU::portWrite(uint2 port, uint8 data) -> void {
status.port[port] = data;
}
Updated to v067r23 release. byuu says: Added missing $4200 IRQ lock, which fixes Chou Aniki on the fast CPU core, so slower PCs can get their brotherly love on. Added range-based controller IOBit latching to the fast CPU core, which enables Super Scope and Justifier support. Uses the priority queue as well, so there is zero speed-hit. Given the way range-testing works, the trigger point may vary by 1-2 pixels when firing at the same spot. Not really a big deal when it avoids a massive speed penalty. Fixed PAL and interlace-mode HVIRQs at V=0,H<2 on the fast CPU core. Added the dot-renderer's sprite list update-on-OAM-write functionality to the scanline-based PPU renderer. Unfortunately it looks like all the speed gain was already taken from the global dirty flag I was using before, but this certainly won't hurt speed any, so whatever. Added #ifdef to stop CoInitialize(0) on non-Windows ports. Added #ifdefs to stop gradient fade on Windows port. Not going to fuck over the Linux port aesthetic because of Qt bug #47,326,927. If there's a way to tell what Qt theme is being used, I can leave it enabled for XP/Vista themes. Moved HDMA trigger from 1104 to 1112, and reduced channel overhead from 24 to 16, to better simulate one-cycle DMA->CPU sync. Code clarity: I've re-added my varint.hpp classes, and am actively using them in the accuracy cores. So far, I haven't done anything that would detriment speed, but it is certainly cool. The APU ports exposed by the CPU and SMP now take uint2 address arguments, the CPU WRAM address register is a uint17, and the IRQ H/VTIME values are uint10. This basically allows the source to clearly convey the data sizes, and eliminates the need to manually mask values when writing to registers or reading from memory. I'm going to be doing this everywhere, and it will have a speed impact eventually, because the automation means we can't skip masks when we know the data is already masked off. Source: archive contains the launcher code, so that I can look into why it's crashing on XP tomorrow. It doesn't look like Circuit USA's flags are going to work too well with this new CPU core. Still not sure what the hell Robocop vs The Terminator is doing, I'll read through the mega SNES thread for clues tomorrow. Speedy Gonzales is definitely broken, as modifying the MDR was breaking things with my current core. Probably because the new CPU core doesn't wait for a cycle edge to trigger. I was thinking that perhaps we could keep some form of cheat codes list to work as game-specific hacks for the performance core. Keeps the hacks out of the emulator, but could allow the remaining bugs to be worked around for people who have no choice but to use the performance core.
2010-08-16 09:42:20 +00:00
auto CPU::op_io() -> void {
status.clock_count = 6;
dma_edge();
add_clocks(6);
alu_edge();
}
auto CPU::op_read(uint24 addr) -> uint8 {
status.clock_count = speed(addr);
dma_edge();
add_clocks(status.clock_count - 4);
regs.mdr = bus.read(addr, regs.mdr);
add_clocks(4);
alu_edge();
debugger.op_read(addr, regs.mdr);
return regs.mdr;
}
auto CPU::op_write(uint24 addr, uint8 data) -> void {
alu_edge();
status.clock_count = speed(addr);
dma_edge();
add_clocks(status.clock_count);
bus.write(addr, regs.mdr = data);
debugger.op_write(addr, regs.mdr);
}
auto CPU::speed(uint24 addr) const -> uint {
if(addr & 0x408000) {
if(addr & 0x800000) return status.rom_speed;
return 8;
}
if((addr + 0x6000) & 0x4000) return 8;
if((addr - 0x4000) & 0x7e00) return 6;
return 12;
}
auto CPU::disassembler_read(uint24 addr) -> uint8 {
return bus.read(addr, regs.mdr);
}