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bsnes/higan/sfc/coprocessor/spc7110/spc7110.cpp

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Update to v088r07 release. byuu says: (r05 and r06 were save points between large core modifications) I would really appreciate extensive regression testing (especially around SuperFX, Cx4, ST018, DSP-n, ST-01n, NES, GB) at this point. The most critical core changes should be completed now. And it was an unbelievable amount of restructuring. Changelog: - SuperFX core moved to Processor::GSU - SNES::CPU core moved to Processor::R65816 - SNES::SMP core moved to Processor::SPC700 - NES::CPU core renamed to Processor::R6502 - use filestream to load RAM files from interface - save states store SHA256 instead of CRC32 (CRC32 usage removed entirely from bsnes) - nes/ -> fc/ and NES -> FC - snes/ -> sfc/ and SNES -> SFC - SuperFamicom::MappedRAM::copy uses stream instead of data+size - Linux port uses gcc-4.7 (still using only gcc-4.6 subset, so you can make a gcc-4.6 symlink for now if you like.) - all profiles and all targets compile and work properly All eight instruction set cores have been moved to processor/ now. Consistency's a wonderful thing. The last remnants of NES/SNES are now limited to target-ui code; and the nall/(system) folder names. I'm building with gcc-4.7 on my Linux box now because the resultant binaries are up to 20% faster (seriously) than gcc-4.6.
2012-04-29 06:16:44 +00:00
#include <sfc/sfc.hpp>
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v088r01 release. byuu says: - GB::CPU::Core -> Processor::LR35902 - Processor::LR35902 -> jump table to switch table - GB::LCD -> GB::PPU - static frequency for DMG (no multiplication on clock ticks) - GB::PPU::interface->videoRefresh() moved outside scheduler (use host thread) - namespace NES -> Famicom - namespace SNES -> SuperFamicom - namespace GB -> GameBoy - namespace GBA -> GameBoyAdvance - removed boot.rom writeout in GB::System
2012-04-26 10:51:13 +00:00
namespace SuperFamicom {
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
#include "dcu.cpp"
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
#include "data.cpp"
#include "alu.cpp"
#include "serialization.cpp"
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
SPC7110 spc7110;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
SPC7110::SPC7110() {
decompressor = new Decompressor(*this);
}
SPC7110::~SPC7110() {
delete decompressor;
}
Update to v097r13 release. byuu says: I refactored my schedulers. Added about ten lines to each scheduler, and removed about 100 lines of calling into internal state in the scheduler for the FC,SFC cores and about 30-40 lines for the other cores. All of its state is now private. Also reworked all of the entry points to static auto Enter() and auto main(). Where Enter() handles all the synchronization stuff, and main() doesn't need the while(true); loop forcing another layer of indentation everywhere. Took a few hours to do, but totally worth it. I'm surprised I didn't do this sooner. Also updated icarus gmake install rule to copy over the database.
2016-02-09 11:51:12 +00:00
auto SPC7110::Enter() -> void {
while(true) scheduler.synchronize(), spc7110.main();
}
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
Update to v097r13 release. byuu says: I refactored my schedulers. Added about ten lines to each scheduler, and removed about 100 lines of calling into internal state in the scheduler for the FC,SFC cores and about 30-40 lines for the other cores. All of its state is now private. Also reworked all of the entry points to static auto Enter() and auto main(). Where Enter() handles all the synchronization stuff, and main() doesn't need the while(true); loop forcing another layer of indentation everywhere. Took a few hours to do, but totally worth it. I'm surprised I didn't do this sooner. Also updated icarus gmake install rule to copy over the database.
2016-02-09 11:51:12 +00:00
auto SPC7110::main() -> void {
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
if(dcuPending) { dcuPending = 0; dcuBeginTransfer(); }
if(mulPending) { mulPending = 0; aluMultiply(); }
if(divPending) { divPending = 0; aluDivide(); }
addClocks(1);
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
auto SPC7110::addClocks(uint clocks) -> void {
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
step(clocks);
Update to v100r14 release. byuu says: (Windows: compile with -fpermissive to silence an annoying error. I'll fix it in the next WIP.) I completely replaced the time management system in higan and overhauled the scheduler. Before, processor threads would have "int64 clock"; and there would be a 1:1 relationship between two threads. When thread A ran for X cycles, it'd subtract X * B.Frequency from clock; and when thread B ran for Y cycles, it'd add Y * A.Frequency from clock. This worked well and allowed perfect precision; but it doesn't work when you have more complicated relationships: eg the 68K can sync to the Z80 and PSG; the Z80 to the 68K and PSG; so the PSG needs two counters. The new system instead uses a "uint64 clock" variable that represents time in attoseconds. Every time the scheduler exits, it subtracts the smallest clock count from all threads, to prevent an overflow scenario. The only real downside is that rounding errors mean that roughly every 20 minutes, we have a rounding error of one clock cycle (one 20,000,000th of a second.) However, this only applies to systems with multiple oscillators, like the SNES. And when you're in that situation ... there's no such thing as a perfect oscillator anyway. A real SNES will be thousands of times less out of spec than 1hz per 20 minutes. The advantages are pretty immense. First, we obviously can now support more complex relationships between threads. Second, we can build a much more abstracted scheduler. All of libco is now abstracted away completely, which may permit a state-machine / coroutine version of Thread in the future. We've basically gone from this: auto SMP::step(uint clocks) -> void { clock += clocks * (uint64)cpu.frequency; dsp.clock -= clocks; if(dsp.clock < 0 && !scheduler.synchronizing()) co_switch(dsp.thread); if(clock >= 0 && !scheduler.synchronizing()) co_switch(cpu.thread); } To this: auto SMP::step(uint clocks) -> void { Thread::step(clocks); synchronize(dsp); synchronize(cpu); } As you can see, we don't have to do multiple clock adjustments anymore. This is a huge win for the SNES CPU that had to update the SMP, DSP, all peripherals and all coprocessors. Likewise, we don't have to synchronize all coprocessors when one runs, now we can just synchronize the active one to the CPU. Third, when changing the frequencies of threads (think SGB speed setting modes, GBC double-speed mode, etc), it no longer causes the "int64 clock" value to be erroneous. Fourth, this results in a fairly decent speedup, mostly across the board. Aside from the GBA being mostly a wash (for unknown reasons), it's about an 8% - 12% speedup in every other emulation core. Now, all of this said ... this was an unbelievably massive change, so ... you know what that means >_> If anyone can help test all types of SNES coprocessors, and some other system games, it'd be appreciated. ---- Lastly, we have a bitchin' new about screen. It unfortunately adds ~200KiB onto the binary size, because the PNG->C++ header file transformation doesn't compress very well, and I want to keep the original resource files in with the higan archive. I might try some things to work around this file size increase in the future, but for now ... yeah, slightly larger archive sizes, sorry. The logo's a bit busted on Windows (the Label control's background transparency and alignment settings aren't working), but works well on GTK. I'll have to fix Windows before the next official release. For now, look on my Twitter feed if you want to see what it's supposed to look like. ---- EDIT: forgot about ICD2::Enter. It's doing some weird inverse run-to-save thing that I need to implement support for somehow. So, save states on the SGB core probably won't work with this WIP.
2016-07-30 03:56:12 +00:00
synchronize(cpu);
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
}
Update to v095r06 release. byuu says: Changelog: - fixed I/O register reads; perfect score on endrift's I/O tests now - fixed mouse capture clipping on Windows [Cydrak] - several hours of code maintenance work done on the SFC core All higan/sfc files should now use the auto fn() -> ret; syntax. Haven't converted all unsigned->uint yet. Also, probably won't do sfc/alt as that's mostly just speed hack stuff. Errata: - forgot auto& instead of just auto on SuperFamicom::Video::draw_cursor, which makes Super Scope / Justifier crash. Will be fixed in the next WIP.
2015-11-14 00:52:51 +00:00
auto SPC7110::unload() -> void {
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
prom.reset();
drom.reset();
ram.reset();
Update to v075 release. byuu says: This release brings improved Super Game Boy emulation, the final SHA256 hashes for the DSP-(1,1B,2,3,4) and ST-(0010,0011) coprocessors, user interface improvements, and major internal code restructuring. Changelog (since v074): - completely rewrote memory sub-system to support 1-byte granularity in XML mapping - removed Memory inheritance and MMIO class completely, any address can be mapped to any function now - SuperFX: removed SuperFXBus : Bus, now implemented manually - SA-1: removed SA1Bus : Bus, now implemented manually - entire bus mapping is now static, happens once on cartridge load - as a result, read/write handlers now handle MMC mapping; slower average case, far faster worst case - namespace memory is no more, RAM arrays are stored inside the chips they are owned by now - GameBoy: improved CPU HALT emulation, fixes Zelda: Link's Awakening scrolling - GameBoy: added serial emulation (cannot connect to another GB yet), fixes Shin Megami Tensei - Devichil - GameBoy: improved LCD STAT emulation, fixes Sagaia - ui: added fullscreen support (F11 key), video settings allows for three scale settings - ui: fixed brightness, contrast, gamma, audio volume, input frequency values on program startup - ui: since Qt is dead, config file becomes bsnes.cfg once again - Super Game Boy: you can now load the BIOS without a game inserted to see a pretty white box - ui-gameboy: can be built without SNES components now - libsnes: now a UI target, compile with 'make ui=ui-libsnes' - libsnes: added WRAM, APURAM, VRAM, OAM, CGRAM access (cheat search, etc) - source: removed launcher/, as the Qt port is now gone - source: Makefile restructuring to better support new ui targets - source: lots of other internal code cleanup work
2011-01-27 08:52:34 +00:00
}
Update to v095r06 release. byuu says: Changelog: - fixed I/O register reads; perfect score on endrift's I/O tests now - fixed mouse capture clipping on Windows [Cydrak] - several hours of code maintenance work done on the SFC core All higan/sfc files should now use the auto fn() -> ret; syntax. Haven't converted all unsigned->uint yet. Also, probably won't do sfc/alt as that's mostly just speed hack stuff. Errata: - forgot auto& instead of just auto on SuperFamicom::Video::draw_cursor, which makes Super Scope / Justifier crash. Will be fixed in the next WIP.
2015-11-14 00:52:51 +00:00
auto SPC7110::power() -> void {
Update to v100r14 release. byuu says: (Windows: compile with -fpermissive to silence an annoying error. I'll fix it in the next WIP.) I completely replaced the time management system in higan and overhauled the scheduler. Before, processor threads would have "int64 clock"; and there would be a 1:1 relationship between two threads. When thread A ran for X cycles, it'd subtract X * B.Frequency from clock; and when thread B ran for Y cycles, it'd add Y * A.Frequency from clock. This worked well and allowed perfect precision; but it doesn't work when you have more complicated relationships: eg the 68K can sync to the Z80 and PSG; the Z80 to the 68K and PSG; so the PSG needs two counters. The new system instead uses a "uint64 clock" variable that represents time in attoseconds. Every time the scheduler exits, it subtracts the smallest clock count from all threads, to prevent an overflow scenario. The only real downside is that rounding errors mean that roughly every 20 minutes, we have a rounding error of one clock cycle (one 20,000,000th of a second.) However, this only applies to systems with multiple oscillators, like the SNES. And when you're in that situation ... there's no such thing as a perfect oscillator anyway. A real SNES will be thousands of times less out of spec than 1hz per 20 minutes. The advantages are pretty immense. First, we obviously can now support more complex relationships between threads. Second, we can build a much more abstracted scheduler. All of libco is now abstracted away completely, which may permit a state-machine / coroutine version of Thread in the future. We've basically gone from this: auto SMP::step(uint clocks) -> void { clock += clocks * (uint64)cpu.frequency; dsp.clock -= clocks; if(dsp.clock < 0 && !scheduler.synchronizing()) co_switch(dsp.thread); if(clock >= 0 && !scheduler.synchronizing()) co_switch(cpu.thread); } To this: auto SMP::step(uint clocks) -> void { Thread::step(clocks); synchronize(dsp); synchronize(cpu); } As you can see, we don't have to do multiple clock adjustments anymore. This is a huge win for the SNES CPU that had to update the SMP, DSP, all peripherals and all coprocessors. Likewise, we don't have to synchronize all coprocessors when one runs, now we can just synchronize the active one to the CPU. Third, when changing the frequencies of threads (think SGB speed setting modes, GBC double-speed mode, etc), it no longer causes the "int64 clock" value to be erroneous. Fourth, this results in a fairly decent speedup, mostly across the board. Aside from the GBA being mostly a wash (for unknown reasons), it's about an 8% - 12% speedup in every other emulation core. Now, all of this said ... this was an unbelievably massive change, so ... you know what that means >_> If anyone can help test all types of SNES coprocessors, and some other system games, it'd be appreciated. ---- Lastly, we have a bitchin' new about screen. It unfortunately adds ~200KiB onto the binary size, because the PNG->C++ header file transformation doesn't compress very well, and I want to keep the original resource files in with the higan archive. I might try some things to work around this file size increase in the future, but for now ... yeah, slightly larger archive sizes, sorry. The logo's a bit busted on Windows (the Label control's background transparency and alignment settings aren't working), but works well on GTK. I'll have to fix Windows before the next official release. For now, look on my Twitter feed if you want to see what it's supposed to look like. ---- EDIT: forgot about ICD2::Enter. It's doing some weird inverse run-to-save thing that I need to implement support for somehow. So, save states on the SGB core probably won't work with this WIP.
2016-07-30 03:56:12 +00:00
create(SPC7110::Enter, 21'477'272);
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4801 = 0x00;
r4802 = 0x00;
r4803 = 0x00;
r4804 = 0x00;
r4805 = 0x00;
r4806 = 0x00;
r4807 = 0x00;
r4809 = 0x00;
r480a = 0x00;
r480b = 0x00;
r480c = 0x00;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
dcuPending = 0;
dcuMode = 0;
dcuAddress = 0;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
r4810 = 0x00;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4811 = 0x00;
r4812 = 0x00;
r4813 = 0x00;
r4814 = 0x00;
r4815 = 0x00;
r4816 = 0x00;
r4817 = 0x00;
r4818 = 0x00;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
r481a = 0x00;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4820 = 0x00;
r4821 = 0x00;
r4822 = 0x00;
r4823 = 0x00;
r4824 = 0x00;
r4825 = 0x00;
r4826 = 0x00;
r4827 = 0x00;
r4828 = 0x00;
r4829 = 0x00;
r482a = 0x00;
r482b = 0x00;
r482c = 0x00;
r482d = 0x00;
r482e = 0x00;
r482f = 0x00;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
mulPending = 0;
divPending = 0;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4830 = 0x00;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
r4831 = 0x00;
r4832 = 0x01;
r4833 = 0x02;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
r4834 = 0x00;
}
Update to v097r15 release. byuu says: Changelog: - higan now uses Natural<Size>/Integer<Size> for its internal types - Super Famicom emulation now uses uint24 instead of uint for bus addresses (it's a 24-bit bus) - cleaned up gb/apu MMIO writes - cleaned up sfc/coprocessor/msu1 MMIO writes - ~3% speed penalty I've wanted to do that 24-bit bus thing for so long, but have always been afraid of the speed impact. It's probably going to hurt balanced/performance once they compile again, but it wasn't significant enough to harm the accuracy core's frame rate, thankfully. Only lost one frame per second. The GBA core handlers are clearly going to take a lot more work. The bit-ranges will make it substantially easier to handle, though. Lots of 32-bit registers where certain values span multiple bytes, but we have to be able to read/write at byte-granularity.
2016-02-16 09:32:49 +00:00
auto SPC7110::read(uint24 addr, uint8 data) -> uint8 {
Update to v100r14 release. byuu says: (Windows: compile with -fpermissive to silence an annoying error. I'll fix it in the next WIP.) I completely replaced the time management system in higan and overhauled the scheduler. Before, processor threads would have "int64 clock"; and there would be a 1:1 relationship between two threads. When thread A ran for X cycles, it'd subtract X * B.Frequency from clock; and when thread B ran for Y cycles, it'd add Y * A.Frequency from clock. This worked well and allowed perfect precision; but it doesn't work when you have more complicated relationships: eg the 68K can sync to the Z80 and PSG; the Z80 to the 68K and PSG; so the PSG needs two counters. The new system instead uses a "uint64 clock" variable that represents time in attoseconds. Every time the scheduler exits, it subtracts the smallest clock count from all threads, to prevent an overflow scenario. The only real downside is that rounding errors mean that roughly every 20 minutes, we have a rounding error of one clock cycle (one 20,000,000th of a second.) However, this only applies to systems with multiple oscillators, like the SNES. And when you're in that situation ... there's no such thing as a perfect oscillator anyway. A real SNES will be thousands of times less out of spec than 1hz per 20 minutes. The advantages are pretty immense. First, we obviously can now support more complex relationships between threads. Second, we can build a much more abstracted scheduler. All of libco is now abstracted away completely, which may permit a state-machine / coroutine version of Thread in the future. We've basically gone from this: auto SMP::step(uint clocks) -> void { clock += clocks * (uint64)cpu.frequency; dsp.clock -= clocks; if(dsp.clock < 0 && !scheduler.synchronizing()) co_switch(dsp.thread); if(clock >= 0 && !scheduler.synchronizing()) co_switch(cpu.thread); } To this: auto SMP::step(uint clocks) -> void { Thread::step(clocks); synchronize(dsp); synchronize(cpu); } As you can see, we don't have to do multiple clock adjustments anymore. This is a huge win for the SNES CPU that had to update the SMP, DSP, all peripherals and all coprocessors. Likewise, we don't have to synchronize all coprocessors when one runs, now we can just synchronize the active one to the CPU. Third, when changing the frequencies of threads (think SGB speed setting modes, GBC double-speed mode, etc), it no longer causes the "int64 clock" value to be erroneous. Fourth, this results in a fairly decent speedup, mostly across the board. Aside from the GBA being mostly a wash (for unknown reasons), it's about an 8% - 12% speedup in every other emulation core. Now, all of this said ... this was an unbelievably massive change, so ... you know what that means >_> If anyone can help test all types of SNES coprocessors, and some other system games, it'd be appreciated. ---- Lastly, we have a bitchin' new about screen. It unfortunately adds ~200KiB onto the binary size, because the PNG->C++ header file transformation doesn't compress very well, and I want to keep the original resource files in with the higan archive. I might try some things to work around this file size increase in the future, but for now ... yeah, slightly larger archive sizes, sorry. The logo's a bit busted on Windows (the Label control's background transparency and alignment settings aren't working), but works well on GTK. I'll have to fix Windows before the next official release. For now, look on my Twitter feed if you want to see what it's supposed to look like. ---- EDIT: forgot about ICD2::Enter. It's doing some weird inverse run-to-save thing that I need to implement support for somehow. So, save states on the SGB core probably won't work with this WIP.
2016-07-30 03:56:12 +00:00
cpu.synchronize(*this);
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
if((addr & 0xff0000) == 0x500000) addr = 0x4800; //$50:0000-ffff == $4800
if((addr & 0xff0000) == 0x580000) addr = 0x4808; //$58:0000-ffff == $4808
addr = 0x4800 | (addr & 0x3f); //$00-3f,80-bf:4800-483f
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
switch(addr) {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==================
//decompression unit
//==================
case 0x4800: {
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
uint16 counter = r4809 | r480a << 8;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
counter--;
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
r4809 = counter >> 0;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
r480a = counter >> 8;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
return dcuRead();
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
case 0x4801: return r4801;
case 0x4802: return r4802;
case 0x4803: return r4803;
case 0x4804: return r4804;
case 0x4805: return r4805;
case 0x4806: return r4806;
case 0x4807: return r4807;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x4808: return 0x00;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4809: return r4809;
case 0x480a: return r480a;
case 0x480b: return r480b;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x480c: return r480c;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==============
//data port unit
//==============
case 0x4810: {
Update to v095r11 release. byuu says: Changelog: - SFC: "uint8 read(uint addr)" -> "uint8 read(uint addr, uint8 data)" - hiro: mHorizontalLayout::setGeometry() return value - hiro/GTK: ListView,TreeView::setFocused() does not grab focus of first item Notes: - nall/windows/utf8.hpp needs using uint = unsigned; at the top to compile - sfc/balanced, sfc/performance won't compile yet Seems Cx4 games broke a while back. Not from this WIP, either. I'll go back and find out what's wrong now.
2015-12-14 09:41:06 +00:00
data = r4810;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
dataPortIncrement4810();
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
return data;
}
case 0x4811: return r4811;
case 0x4812: return r4812;
case 0x4813: return r4813;
case 0x4814: return r4814;
case 0x4815: return r4815;
case 0x4816: return r4816;
case 0x4817: return r4817;
case 0x4818: return r4818;
case 0x481a: {
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
dataPortIncrement481a();
Update to v089r04 release. byuu says: Changelog: (SPC7110) - emulated $480b.d0 + $4807 deinterleave mode - cleaned up decompression core (I'd still like to wipe out those static variables, those are bad for save states.) - improved emulation of data port ($481a only increments, never reads) - improved emulation of RTC (block appropriate bits in the hour register based on 12/24h mode select; $4840 modes != 1 all disable the chip; added MDR; etc.)
2012-05-19 06:28:54 +00:00
return 0x00;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//=====================
//arithmetic logic unit
//=====================
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4820: return r4820;
case 0x4821: return r4821;
case 0x4822: return r4822;
case 0x4823: return r4823;
case 0x4824: return r4824;
case 0x4825: return r4825;
case 0x4826: return r4826;
case 0x4827: return r4827;
case 0x4828: return r4828;
case 0x4829: return r4829;
case 0x482a: return r482a;
case 0x482b: return r482b;
case 0x482c: return r482c;
case 0x482d: return r482d;
case 0x482e: return r482e;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x482f: return r482f;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//memory control unit
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
case 0x4830: return r4830;
case 0x4831: return r4831;
case 0x4832: return r4832;
case 0x4833: return r4833;
case 0x4834: return r4834;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v095r11 release. byuu says: Changelog: - SFC: "uint8 read(uint addr)" -> "uint8 read(uint addr, uint8 data)" - hiro: mHorizontalLayout::setGeometry() return value - hiro/GTK: ListView,TreeView::setFocused() does not grab focus of first item Notes: - nall/windows/utf8.hpp needs using uint = unsigned; at the top to compile - sfc/balanced, sfc/performance won't compile yet Seems Cx4 games broke a while back. Not from this WIP, either. I'll go back and find out what's wrong now.
2015-12-14 09:41:06 +00:00
return data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v097r15 release. byuu says: Changelog: - higan now uses Natural<Size>/Integer<Size> for its internal types - Super Famicom emulation now uses uint24 instead of uint for bus addresses (it's a 24-bit bus) - cleaned up gb/apu MMIO writes - cleaned up sfc/coprocessor/msu1 MMIO writes - ~3% speed penalty I've wanted to do that 24-bit bus thing for so long, but have always been afraid of the speed impact. It's probably going to hurt balanced/performance once they compile again, but it wasn't significant enough to harm the accuracy core's frame rate, thankfully. Only lost one frame per second. The GBA core handlers are clearly going to take a lot more work. The bit-ranges will make it substantially easier to handle, though. Lots of 32-bit registers where certain values span multiple bytes, but we have to be able to read/write at byte-granularity.
2016-02-16 09:32:49 +00:00
auto SPC7110::write(uint24 addr, uint8 data) -> void {
Update to v100r14 release. byuu says: (Windows: compile with -fpermissive to silence an annoying error. I'll fix it in the next WIP.) I completely replaced the time management system in higan and overhauled the scheduler. Before, processor threads would have "int64 clock"; and there would be a 1:1 relationship between two threads. When thread A ran for X cycles, it'd subtract X * B.Frequency from clock; and when thread B ran for Y cycles, it'd add Y * A.Frequency from clock. This worked well and allowed perfect precision; but it doesn't work when you have more complicated relationships: eg the 68K can sync to the Z80 and PSG; the Z80 to the 68K and PSG; so the PSG needs two counters. The new system instead uses a "uint64 clock" variable that represents time in attoseconds. Every time the scheduler exits, it subtracts the smallest clock count from all threads, to prevent an overflow scenario. The only real downside is that rounding errors mean that roughly every 20 minutes, we have a rounding error of one clock cycle (one 20,000,000th of a second.) However, this only applies to systems with multiple oscillators, like the SNES. And when you're in that situation ... there's no such thing as a perfect oscillator anyway. A real SNES will be thousands of times less out of spec than 1hz per 20 minutes. The advantages are pretty immense. First, we obviously can now support more complex relationships between threads. Second, we can build a much more abstracted scheduler. All of libco is now abstracted away completely, which may permit a state-machine / coroutine version of Thread in the future. We've basically gone from this: auto SMP::step(uint clocks) -> void { clock += clocks * (uint64)cpu.frequency; dsp.clock -= clocks; if(dsp.clock < 0 && !scheduler.synchronizing()) co_switch(dsp.thread); if(clock >= 0 && !scheduler.synchronizing()) co_switch(cpu.thread); } To this: auto SMP::step(uint clocks) -> void { Thread::step(clocks); synchronize(dsp); synchronize(cpu); } As you can see, we don't have to do multiple clock adjustments anymore. This is a huge win for the SNES CPU that had to update the SMP, DSP, all peripherals and all coprocessors. Likewise, we don't have to synchronize all coprocessors when one runs, now we can just synchronize the active one to the CPU. Third, when changing the frequencies of threads (think SGB speed setting modes, GBC double-speed mode, etc), it no longer causes the "int64 clock" value to be erroneous. Fourth, this results in a fairly decent speedup, mostly across the board. Aside from the GBA being mostly a wash (for unknown reasons), it's about an 8% - 12% speedup in every other emulation core. Now, all of this said ... this was an unbelievably massive change, so ... you know what that means >_> If anyone can help test all types of SNES coprocessors, and some other system games, it'd be appreciated. ---- Lastly, we have a bitchin' new about screen. It unfortunately adds ~200KiB onto the binary size, because the PNG->C++ header file transformation doesn't compress very well, and I want to keep the original resource files in with the higan archive. I might try some things to work around this file size increase in the future, but for now ... yeah, slightly larger archive sizes, sorry. The logo's a bit busted on Windows (the Label control's background transparency and alignment settings aren't working), but works well on GTK. I'll have to fix Windows before the next official release. For now, look on my Twitter feed if you want to see what it's supposed to look like. ---- EDIT: forgot about ICD2::Enter. It's doing some weird inverse run-to-save thing that I need to implement support for somehow. So, save states on the SGB core probably won't work with this WIP.
2016-07-30 03:56:12 +00:00
cpu.synchronize(*this);
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
if((addr & 0xff0000) == 0x500000) addr = 0x4800; //$50:0000-ffff == $4800
if((addr & 0xff0000) == 0x580000) addr = 0x4808; //$58:0000-ffff == $4808
addr = 0x4800 | (addr & 0x3f); //$00-3f,80-bf:4800-483f
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
switch(addr) {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==================
//decompression unit
//==================
case 0x4801: r4801 = data; break;
case 0x4802: r4802 = data; break;
Update to v089r10 release. byuu says: Changelog: - Cydrak merged all three SPC7110 decompression routines into one, cuts the size in half - fixed masking of $4803.d7 and $4813.d7 - data port out of bounds accesses emulated correctly for app SPC7110 boards - all(?) data port $4810 reload cases now supported - basic timing for $4805-6 seeking; reworked delay timing to work better as well - fixed $480c.d7 flag (1 = ready, not busy) - AbsoluteInput returns -32768 if presentation window lacks focus and you don't always allow input
2012-05-31 12:27:46 +00:00
case 0x4803: r4803 = data; break;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
case 0x4804: r4804 = data; dcuLoadAddress(); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4805: r4805 = data; break;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
case 0x4806: r4806 = data; r480c &= 0x7f; dcuPending = 1; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4807: r4807 = data; break;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x4808: break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4809: r4809 = data; break;
case 0x480a: r480a = data; break;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x480b: r480b = data & 0x03; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//==============
//data port unit
//==============
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x4811: r4811 = data; break;
case 0x4812: r4812 = data; break;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
case 0x4813: r4813 = data; dataPortRead(); break;
case 0x4814: r4814 = data; dataPortIncrement4814(); break;
case 0x4815: r4815 = data; if(r4818 & 2) dataPortRead(); dataPortIncrement4815(); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4816: r4816 = data; break;
case 0x4817: r4817 = data; break;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
case 0x4818: r4818 = data & 0x7f; dataPortRead(); break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//=====================
//arithmetic logic unit
//=====================
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4820: r4820 = data; break;
case 0x4821: r4821 = data; break;
case 0x4822: r4822 = data; break;
case 0x4823: r4823 = data; break;
case 0x4824: r4824 = data; break;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
case 0x4825: r4825 = data; r482f |= 0x81; mulPending = 1; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
case 0x4826: r4826 = data; break;
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
case 0x4827: r4827 = data; r482f |= 0x80; divPending = 1; break;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
case 0x482e: r482e = data & 0x01; break;
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
Update to v089r09 release. byuu says: Changelog: - SPC7110 data port emulation greatly improved - SPC7110 $480b.d1 emulated (but $4805-4806 does not work right for mode 2 decompression yet) - MSU1 audio output will be muted when the S-DSP FLG ($6c).d6 (mute) flag is set - MSU1 will read filenames from manifest now (defaults to msu1.rom and track-#.pcm if missing ... for now) - bugfixes with MSU1 load state and track seek (and $4804 was wrapping into $4805 to change the track#) - Link coprocessor removed (it was meant for ST018 HLE, which never happened) Notes for things I forgot but need to address: - $4813 needs to be uint7 for the set_data_offset() to not allow reading A23 as set ever (or we can mask) - AbsoluteInput when window doesn't have focus should return -32768, not 0 - need to support input ID lists that aren't linear (0-7), but arbitrary (0,1,6,7 or whatever)
2012-05-29 12:20:46 +00:00
//memory control unit
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===================
case 0x4830: r4830 = data & 0x87; break;
case 0x4831: r4831 = data & 0x07; break;
case 0x4832: r4832 = data & 0x07; break;
case 0x4833: r4833 = data & 0x07; break;
case 0x4834: r4834 = data & 0x07; break;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
}
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
//===============
//SPC7110::MCUROM
//===============
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
//map address=00-3f,80-bf:8000-ffff mask=0x800000 => 00-3f:8000-ffff
//map address=c0-ff:0000-ffff mask=0xc00000 => c0-ff:0000-ffff
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
auto SPC7110::mcuromRead(uint24 addr, uint8 data) -> uint8 {
Update to v095r06 release. byuu says: Changelog: - fixed I/O register reads; perfect score on endrift's I/O tests now - fixed mouse capture clipping on Windows [Cydrak] - several hours of code maintenance work done on the SFC core All higan/sfc files should now use the auto fn() -> ret; syntax. Haven't converted all unsigned->uint yet. Also, probably won't do sfc/alt as that's mostly just speed hack stuff. Errata: - forgot auto& instead of just auto on SuperFamicom::Video::draw_cursor, which makes Super Scope / Justifier crash. Will be fixed in the next WIP.
2015-11-14 00:52:51 +00:00
uint mask = (1 << (r4834 & 3)) - 1; //8mbit, 16mbit, 32mbit, 64mbit DROM
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
if(addr < 0x100000) { //$00-0f,80-8f:8000-ffff; $c0-cf:0000-ffff
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
addr &= 0x0fffff;
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
if(prom.size()) { //8mbit PROM
return prom.read(bus.mirror(0x000000 + addr, prom.size()));
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4830 & 7);
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
return dataromRead(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
if(addr < 0x200000) { //$10-1f,90-9f:8000-ffff; $d0-df:0000-ffff
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
addr &= 0x0fffff;
if(r4834 & 4) { //16mbit PROM
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
return prom.read(bus.mirror(0x100000 + addr, prom.size()));
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4831 & 7);
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
return dataromRead(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
if(addr < 0x300000) { //$20-2f,a0-af:8000-ffff; $e0-ef:0000-ffff
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
addr &= 0x0fffff;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4832 & 7);
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
return dataromRead(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
if(addr < 0x400000) { //$30-3f,b0-bf:8000-ffff; $f0-ff:0000-ffff
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
addr &= 0x0fffff;
Update to v089r03 release. byuu says: Substantial improvements to SPC7110 emulation. Added all of the findings from http://byuu.org/temp/spc7110-mmio.txt that I understood. I also completely rewrote the RTC. We only had about ~40% of the chip emulated before. Turns out there's cool stuff like spare RAM, calendar disable, 12-hour mode, IRQs, IRQ masking, duty cycles, etc. So I went ahead and emulated all of it. The upper bits on hour+ don't work as nocash described though, not sure what doc he was reading. The Epson RTC-4513 manual I have doesn't explain any of the registers. The new RTC core also ticks seconds based on the emulated clock, and not on the system clock. This is going to suck for people wanting to keep the in-game clock synced with their computer, who also abuse fast forward and save states. Fast forward makes the clock run faster, and save states will jump the clock to the time it was at when you took the save state. (It will keep track of the number of seconds between unloading the game and loading it again, so time passes normally there.) This is required, however, and how I'm going to rearrange all of the RTCs for all systems. Any other method can be detected by the game, and is thus not faithful emulation. To help with this, I'll probably make an RTC time tool so that you can adjust the time when the emulator isn't running, but I don't intend to bundle that into bsnes. New state format bit-packs the RTCRAM values, and it also uses a 64-bit timestamp. So it's 16 bytes now instead of 20 bytes. S-RTC will drop from 16 to 12 when it's done. The RTC busy flag timing needs to be refined with more hardware tests, there's a slim chance of the game hanging on save at the moment. The SPC7110 ALU delays are emulated now, too. They may not be perfectly accurate, but they get the basic gist down. The only hack that needs to be removed now is the decompression busy flag. That's ... not going to be fun. I also redid the mouse emulation. I was polling the mouse position multiple times per latch. So it should be a bit more precise now, I hope. I read it regardless of latch state, dunno if that's good or not.
2012-05-16 00:27:34 +00:00
addr |= 0x100000 * (r4833 & 7);
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
return dataromRead(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
Update to v095r11 release. byuu says: Changelog: - SFC: "uint8 read(uint addr)" -> "uint8 read(uint addr, uint8 data)" - hiro: mHorizontalLayout::setGeometry() return value - hiro/GTK: ListView,TreeView::setFocused() does not grab focus of first item Notes: - nall/windows/utf8.hpp needs using uint = unsigned; at the top to compile - sfc/balanced, sfc/performance won't compile yet Seems Cx4 games broke a while back. Not from this WIP, either. I'll go back and find out what's wrong now.
2015-12-14 09:41:06 +00:00
return data;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
auto SPC7110::mcuromWrite(uint24 addr, uint8 data) -> void {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
//===============
//SPC7110::MCURAM
//===============
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
//map address=00-3f,80-bf:6000-7fff mask=0x80e000 => 00-07:0000-ffff
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
auto SPC7110::mcuramRead(uint24 addr, uint8) -> uint8 {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
if(r4830 & 0x80) {
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
addr = bus.mirror(addr, ram.size());
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
return ram.read(addr);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
return 0x00;
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
Update to v099r03 release. byuu says: Changelog: - finished cleaning up the SFC core to my new coding conventions - removed sfc/controller/usart (superseded by 21fx) - hid Synchronize Video option from the menu (still in the configuration file) Pretty much the only minor detail left is some variable names in the SA-1 core that really won't look good at all if I move to camelCase, so I'll have to rethink how I handle those. It's probably a good area to attempt using BitFields, to see how it impacts performance. But I'll do that in a test branch first. But for the most part, this should be the end of the gigantic diffs (this one was 174KiB), at least for the SFC/WS cores. Still have the FC/GB/GBA cores to clean up more fully. Assuming we don't spot any new regressions, we should be ~95% out of the woods on code cleanups breaking things.
2016-06-17 13:03:54 +00:00
auto SPC7110::mcuramWrite(uint24 addr, uint8 data) -> void {
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
if(r4830 & 0x80) {
Update to higan and icarus v095r15 release. r13 and r14 weren't posted as individual releases, but their changelogs were posted. byuu says about r13: I'm not going to be posting WIPs for r13 and above for a while. The reason is that I'm working on the major manifest overhaul I've discussed previously on the icarus subforum. I'm recreating my boards database from scratch using the map files and the new map analyzer. The only games that will load are ones I've created board definitions for, and updated sfc/cartridge/markup.cpp to parse. Once I've finished all the boards, then I'll update the heuristics. Then finally, I'll sync the syntax changes over to the fc, gb, gba cores. Once that's done, I'll start posting WIPs again, along with a new build of icarus. But I'll still post changelogs as I work through things. Changelog (r13): - preservation: created new database-builder tool (merges region-specific databases with boards) - icarus: support new, external database format (~/.config/icarus/Database/(Super Famicom.bml, ...) - added 1A3B-(10,11,12); 1A3B-20 byuu says about r14: r14 work: I successfully created mappings for every board used in the US set. I also updated icarus' heuristics to use the new mappings, and created ones there for the boards that are only in the JP set. Then I patched icarus to support pulling games out of the database when it's used on a game folder to generate a manifest file. Then I updated a lot of code in higan/sfc to support the new mapping syntax. sfc/cartridge/markup.cpp is about half the size it used to be with the new mappings, and I was able to kill off both map/id and map/select entirely. Then I updated all four emulated systems (and both subsystems) to use "board" as the root node, and harmonized their syntax (made them all more consistent with each other.) Then I added a manifest viewer to the tools window+menu. It's kind of an advanced user feature, but oh well. No reason to coddle people when the feature is very useful for developers. The viewer will show all manifests in order when you load multi-cart games as well. Still not going to call any syntax 100% done right now, but thankfully with the new manifest-free folders, nobody will have to do anything to use the new format. Just download the new version and go. The Super Famicom Event stuff is currently broken (CC92/PF94 boards). That's gonna be fun to support. byuu says about r15: EDIT: small bug in icarus with heuristics. Edit core/super-famicom.cpp line 27: if(/*auto*/ markup = cartridge.markup) { Gotta remove that "auto" so that it returns valid markup. Resolved the final concerns I had with the new manifest format. Right now there are two things that are definitely broken: MCC (BS-X Town cart) and Event (CC '92 and PF'94). And there are a few things that are untested: SPC7110, EpsonRTC, SharpRTC, SDD1+RAM, SufamiTurbo, BS-X slotted carts.
2015-12-19 08:52:34 +00:00
addr = bus.mirror(addr, ram.size());
Update to v089r15 release. byuu says: Changelog: - SuperFX has its own ROM and RAM - Cx4 has its own ROM - SPC7110 has its own ProgramROM, DataROM and RAM - OBC1 has its own RAM - BsxCartridge has its own ROM, RAM and PSRAM - mapping changes to accommodate the above
2012-07-09 11:40:23 +00:00
ram.write(addr, data);
Update to v089r02 release. (r01 was not posted to the WIP thread) byuu says: r01 changelog: - major improvements to SPC7110 MCU (memory controller unit) - revised SPC7110 memory map to reflect aforementioned improvements - added "Toggle Tracer" hotkey to target-ethos (only works for SFC so far, I plan to use this as a lightweight laevateinn for FEoEZ) r02 changelog: - quick fix: SRAM is mapped to 00-3f|80-bf:6000-7fff - quick fix: $4830.d7 is SRAM chip enable, not SRAM write enable. Reads return 0x00 when this bit is clear
2012-05-14 13:32:55 +00:00
}
First version split into asnes and bsnes.
2010-08-09 13:28:56 +00:00
}
}