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BizHawk/BizHawk.Emulation.Cores/CPUs/Z80A
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alyosha-tas 258688ebdd Add files via upload 2017-10-13 11:07:02 -04:00
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Execute.cs Add files via upload 2017-10-13 11:07:02 -04:00
Interrupts.cs Add files via upload 2017-10-12 20:20:13 -04:00
NewDisassembler.cs Add files via upload 2017-10-12 20:20:13 -04:00
Operations.cs Add files via upload 2017-10-13 11:07:02 -04:00
ReadMe.txt Create ReadMe.txt 2017-10-12 20:19:42 -04:00
Registers.cs Add files via upload 2017-10-12 20:20:13 -04:00
Tables_Direct.cs Add files via upload 2017-10-12 20:20:13 -04:00
Tables_Indirect.cs Add files via upload 2017-10-12 20:20:13 -04:00
Z80A.cs Add files via upload 2017-10-13 11:07:02 -04:00

ReadMe.txt 

TODO: 

Mode 0 and 2 interrupts
Check T-cycle level memory access timing
Check R register 
new tests for WZ Registers
Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?
Data Bus - For mode zero and 2 interrupts, need a system that uses it to test