BizHawk/BizHawk.Emulation.Cores/CPUs/Z80A
alyosha-tas 7cdffc25c3
Update Z80A.cs
Properly reset instruction vector index
2017-11-03 08:39:02 -04:00
..
Execute.cs Z80: Fix R register operation 2017-10-19 12:08:34 -04:00
Interrupts.cs Add files via upload 2017-10-13 17:58:36 -04:00
NewDisassembler.cs Z80: Fix CDL 2017-10-25 19:21:30 -04:00
Operations.cs Z80 2017-10-14 14:07:17 -04:00
ReadMe.txt Create ReadMe.txt 2017-10-12 20:19:42 -04:00
Registers.cs Add files via upload 2017-10-13 17:58:36 -04:00
Tables_Direct.cs Z80: Fix R register operation 2017-10-19 12:08:34 -04:00
Tables_Indirect.cs Add files via upload 2017-10-13 17:58:36 -04:00
Z80A.cs Update Z80A.cs 2017-11-03 08:39:02 -04:00

ReadMe.txt

TODO: 

Mode 0 and 2 interrupts
Check T-cycle level memory access timing
Check R register 
new tests for WZ Registers
Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this?
Data Bus - For mode zero and 2 interrupts, need a system that uses it to test