a9f8828063
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| .. | ||
| Execute.cs | ||
| Interrupts.cs | ||
| NewDisassembler.cs | ||
| Operations.cs | ||
| ReadMe.txt | ||
| Registers.cs | ||
| Tables_Direct.cs | ||
| Tables_Indirect.cs | ||
| Z80A.cs | ||
ReadMe.txt
TODO: Mode 0 and 2 interrupts Check T-cycle level memory access timing Check R register new tests for WZ Registers Memory refresh - IR is pushed onto the address bus at instruction start, does anything need this? Data Bus - For mode zero and 2 interrupts, need a system that uses it to test