701 lines
19 KiB
C#
701 lines
19 KiB
C#
using System;
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using System.Globalization;
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using System.IO;
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using BizHawk.Common;
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using BizHawk.Emulation.Common;
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using BizHawk.Common.NumberExtensions;
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// Z80A CPU
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namespace BizHawk.Emulation.Cores.Components.Z80A
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{
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public sealed partial class Z80A
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{
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// operations that can take place in an instruction
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public const ushort IDLE = 0;
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public const ushort OP = 1;
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public const ushort OP_R = 2; // used for repeating operations
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public const ushort HALT = 3;
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public const ushort RD = 4;
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public const ushort WR = 5;
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public const ushort I_RD = 6;
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public const ushort I_WR = 7;
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public const ushort TR = 8;
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public const ushort TR16 = 9;
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public const ushort ADD16 = 10;
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public const ushort ADD8 = 11;
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public const ushort SUB8 = 12;
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public const ushort ADC8 = 13;
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public const ushort SBC8 = 14;
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public const ushort SBC16 = 15;
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public const ushort ADC16 = 16;
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public const ushort INC16 = 17;
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public const ushort INC8 = 18;
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public const ushort DEC16 = 19;
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public const ushort DEC8 = 20;
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public const ushort RLC = 21;
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public const ushort RL = 22;
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public const ushort RRC = 23;
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public const ushort RR = 24;
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public const ushort CPL = 25;
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public const ushort DA = 26;
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public const ushort SCF = 27;
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public const ushort CCF = 28;
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public const ushort AND8 = 29;
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public const ushort XOR8 = 30;
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public const ushort OR8 = 31;
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public const ushort CP8 = 32;
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public const ushort SLA = 33;
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public const ushort SRA = 34;
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public const ushort SRL = 35;
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public const ushort SLL = 36;
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public const ushort BIT = 37;
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public const ushort RES = 38;
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public const ushort SET = 39;
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public const ushort EI = 40;
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public const ushort DI = 41;
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public const ushort EXCH = 42;
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public const ushort EXX = 43;
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public const ushort EXCH_16 = 44;
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public const ushort PREFIX = 45;
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public const ushort PREFETCH = 46;
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public const ushort ASGN = 47;
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public const ushort ADDS = 48; // signed 16 bit operation used in 2 instructions
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public const ushort INT_MODE = 49;
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public const ushort EI_RETN = 50;
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public const ushort EI_RETI = 51; // reti has no delay in interrupt enable
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public const ushort OUT = 52;
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public const ushort IN = 53;
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public const ushort NEG = 54;
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public const ushort RRD = 55;
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public const ushort RLD = 56;
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public const ushort SET_FL_LD = 57;
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public const ushort SET_FL_CP = 58;
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public const ushort SET_FL_IR = 59;
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public const ushort I_BIT = 60;
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public const ushort HL_BIT = 61;
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public const ushort FTCH_DB = 62;
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public byte temp_R;
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public Z80A()
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{
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Reset();
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InitTableParity();
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}
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public void Reset()
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{
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ResetRegisters();
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ResetInterrupts();
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TotalExecutedCycles = 0;
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cur_instr = new ushort[] { OP };
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instr_pntr = 0;
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NO_prefix = true;
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}
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public IMemoryCallbackSystem MemoryCallbacks { get; set; }
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// Memory Access
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public Func<ushort, byte> FetchMemory;
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public Func<ushort, byte> ReadMemory;
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public Action<ushort, byte> WriteMemory;
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public Func<ushort, byte> PeekMemory;
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public Func<ushort, byte> DummyReadMemory;
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// Hardware I/O Port Access
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public Func<ushort, byte> ReadHardware;
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public Action<ushort, byte> WriteHardware;
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// Data BUs
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// Interrupting Devices are responsible for putting a value onto the data bus
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// for as long as the interrupt is valid
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public Func<byte> FetchDB;
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//this only calls when the first byte of an instruction is fetched.
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public Action<ushort> OnExecFetch;
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public void UnregisterMemoryMapper()
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{
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ReadMemory = null;
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WriteMemory = null;
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PeekMemory = null;
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DummyReadMemory = null;
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ReadHardware = null;
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WriteHardware = null;
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}
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public void SetCallbacks
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(
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Func<ushort, byte> ReadMemory,
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Func<ushort, byte> DummyReadMemory,
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Func<ushort, byte> PeekMemory,
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Action<ushort, byte> WriteMemory,
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Func<ushort, byte> ReadHardware,
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Action<ushort, byte> WriteHardware
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)
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{
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this.ReadMemory = ReadMemory;
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this.DummyReadMemory = DummyReadMemory;
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this.PeekMemory = PeekMemory;
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this.WriteMemory = WriteMemory;
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this.ReadHardware = ReadHardware;
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this.WriteHardware = WriteHardware;
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}
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// Execute instructions
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public void ExecuteOne()
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{
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if (Regs[A] > 255) { Console.WriteLine(RegPC); }
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switch (cur_instr[instr_pntr++])
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{
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case IDLE:
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// do nothing
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break;
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case OP:
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// Read the opcode of the next instruction
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if (EI_pending > 0)
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{
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EI_pending--;
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if (EI_pending == 0) { IFF1 = IFF2 = true; }
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}
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// Process interrupt requests.
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if (nonMaskableInterruptPending)
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{
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nonMaskableInterruptPending = false;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo{Disassembly = "====NMI====", RegisterInfo = ""});
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}
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iff2 = iff1;
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iff1 = false;
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NMI_();
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NMICallback();
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}
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else if (iff1 && FlagI)
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{
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iff1 = iff2 = false;
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EI_pending = 0;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo{Disassembly = "====IRQ====", RegisterInfo = ""});
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}
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switch (interruptMode)
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{
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case 0:
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// Requires something to be pushed onto the data bus
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// we'll assume it's a zero for now
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INTERRUPT_0(0);
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break;
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case 1:
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INTERRUPT_1();
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break;
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case 2:
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// Low byte of interrupt vector comes from data bus
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// We'll assume it's zero for now
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INTERRUPT_2(0);
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break;
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}
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IRQCallback();
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}
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else
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{
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null) TraceCallback(State());
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FetchInstruction(FetchMemory(RegPC++));
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}
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instr_pntr = 0;
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temp_R = (byte)(Regs[R] & 0x7F);
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temp_R++;
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temp_R &= 0x7F;
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Regs[R] = (byte)((Regs[R] & 0x80) | temp_R);
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break;
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case OP_R:
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// determine if we repeat based on what operation we are doing
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// single execution versions also come here, but never repeat
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ushort temp1 = cur_instr[instr_pntr++];
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ushort temp2 = cur_instr[instr_pntr++];
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ushort temp3 = cur_instr[instr_pntr++];
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bool repeat = false;
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int Reg16_d = Regs[C] | (Regs[B] << 8);
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switch (temp1)
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{
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case 0:
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repeat = Reg16_d != 0;
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break;
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case 1:
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repeat = (Reg16_d != 0) && !FlagZ;
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break;
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case 2:
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repeat = Regs[B] != 0;
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break;
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case 3:
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repeat = Regs[B] != 0;
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break;
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}
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// if we repeat, we do a 5 cycle refresh which decrements PC by 2
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// if we don't repeat, continue on as a normal opcode fetch
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if (repeat && temp3 > 0)
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{
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cur_instr = new ushort[]
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{IDLE,
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DEC16, PCl, PCh,
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IDLE,
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DEC16, PCl, PCh,
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OP };
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// adjust WZ register accordingly
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switch (temp1)
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{
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case 0:
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// TEST: PC before or after the instruction?
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Regs[Z] = Regs[PCl];
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Regs[W] = Regs[PCh];
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INC16_Func(Z, W);
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break;
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case 1:
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// TEST: PC before or after the instruction?
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Regs[Z] = Regs[PCl];
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Regs[W] = Regs[PCh];
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INC16_Func(Z, W);
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break;
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case 2:
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// Nothing
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break;
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case 3:
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// Nothing
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break;
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}
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}
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else
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{
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// Interrupts can occur at this point, so process them accordingly
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// Read the opcode of the next instruction
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if (EI_pending > 0)
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{
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EI_pending--;
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if (EI_pending == 0) { IFF1 = IFF2 = true; }
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}
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// Process interrupt requests.
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if (nonMaskableInterruptPending)
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{
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nonMaskableInterruptPending = false;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo{Disassembly = "====NMI====", RegisterInfo = ""});
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}
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iff2 = iff1;
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iff1 = false;
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NMI_();
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NMICallback();
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}
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else if (iff1 && FlagI)
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{
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iff1 = iff2 = false;
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EI_pending = 0;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo{Disassembly = "====IRQ====", RegisterInfo = ""});
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}
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switch (interruptMode)
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{
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case 0:
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// Requires something to be pushed onto the data bus
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// we'll assume it's a zero for now
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INTERRUPT_0(0);
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break;
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case 1:
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INTERRUPT_1();
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break;
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case 2:
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// Low byte of interrupt vector comes from data bus
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// We'll assume it's zero for now
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INTERRUPT_2(0);
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break;
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}
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IRQCallback();
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}
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else
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{
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if (OnExecFetch != null) OnExecFetch(RegPC);
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if (TraceCallback != null) TraceCallback(State());
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FetchInstruction(FetchMemory(RegPC++));
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}
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temp_R = (byte)(Regs[R] & 0x7F);
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temp_R++;
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temp_R &= 0x7F;
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Regs[R] = (byte)((Regs[R] & 0x80) | temp_R);
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}
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instr_pntr = 0;
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break;
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case HALT:
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halted = true;
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// NOTE: Check how halt state effects the DB
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Regs[DB] = 0xFF;
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if (EI_pending > 0)
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{
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EI_pending--;
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if (EI_pending == 0) { IFF1 = IFF2 = true; }
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}
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// Process interrupt requests.
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if (nonMaskableInterruptPending)
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{
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nonMaskableInterruptPending = false;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo{Disassembly = "====NMI====", RegisterInfo = ""});
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}
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iff2 = iff1;
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iff1 = false;
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NMI_();
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NMICallback();
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halted = false;
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}
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else if (iff1 && FlagI)
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{
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iff1 = iff2 = false;
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EI_pending = 0;
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if (TraceCallback != null)
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{
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TraceCallback(new TraceInfo{Disassembly = "====IRQ====", RegisterInfo = ""});
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}
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switch (interruptMode)
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{
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case 0:
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// Requires something to be pushed onto the data bus
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// we'll assume it's a zero for now
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INTERRUPT_0(0);
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break;
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case 1:
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INTERRUPT_1();
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break;
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case 2:
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// Low byte of interrupt vector comes from data bus
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// We'll assume it's zero for now
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INTERRUPT_2(0);
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break;
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}
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IRQCallback();
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halted = false;
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}
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else
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{
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cur_instr = new ushort[]
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{IDLE,
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IDLE,
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IDLE,
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HALT };
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}
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temp_R = (byte)(Regs[R] & 0x7F);
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temp_R++;
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temp_R &= 0x7F;
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Regs[R] = (byte)((Regs[R] & 0x80) | temp_R);
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instr_pntr = 0;
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break;
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case RD:
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Read_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case WR:
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Write_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case I_RD:
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I_Read_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case I_WR:
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I_Write_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case TR:
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TR_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case TR16:
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TR16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADD16:
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ADD16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADD8:
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ADD8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SUB8:
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SUB8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADC8:
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ADC8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case ADC16:
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ADC_16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SBC8:
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SBC8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SBC16:
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SBC_16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case INC16:
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INC16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case INC8:
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INC8_Func(cur_instr[instr_pntr++]);
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break;
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case DEC16:
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DEC16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case DEC8:
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DEC8_Func(cur_instr[instr_pntr++]);
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break;
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case RLC:
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RLC_Func(cur_instr[instr_pntr++]);
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break;
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case RL:
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RL_Func(cur_instr[instr_pntr++]);
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break;
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case RRC:
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RRC_Func(cur_instr[instr_pntr++]);
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break;
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case RR:
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RR_Func(cur_instr[instr_pntr++]);
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break;
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case CPL:
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CPL_Func(cur_instr[instr_pntr++]);
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break;
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case DA:
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DA_Func(cur_instr[instr_pntr++]);
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break;
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case SCF:
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SCF_Func(cur_instr[instr_pntr++]);
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break;
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case CCF:
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CCF_Func(cur_instr[instr_pntr++]);
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break;
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case AND8:
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AND8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case XOR8:
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XOR8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case OR8:
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OR8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case CP8:
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CP8_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SLA:
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SLA_Func(cur_instr[instr_pntr++]);
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break;
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case SRA:
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SRA_Func(cur_instr[instr_pntr++]);
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break;
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case SRL:
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SRL_Func(cur_instr[instr_pntr++]);
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break;
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case SLL:
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SLL_Func(cur_instr[instr_pntr++]);
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break;
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case BIT:
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BIT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case I_BIT:
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I_BIT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case RES:
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RES_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case SET:
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SET_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
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break;
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case EI:
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EI_pending = 2;
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break;
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case DI:
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IFF1 = IFF2 = false;
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break;
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case EXCH:
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EXCH_16_Func(F_s, A_s, F, A);
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break;
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case EXX:
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EXCH_16_Func(C_s, B_s, C, B);
|
|
EXCH_16_Func(E_s, D_s, E, D);
|
|
EXCH_16_Func(L_s, H_s, L, H);
|
|
break;
|
|
case EXCH_16:
|
|
EXCH_16_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case PREFIX:
|
|
ushort prefix_src = cur_instr[instr_pntr++];
|
|
NO_prefix = false;
|
|
if (prefix_src == CBpre) { CB_prefix = true; }
|
|
if (prefix_src == EXTDpre) { EXTD_prefix = true; }
|
|
if (prefix_src == IXpre) { IX_prefix = true; }
|
|
if (prefix_src == IYpre) { IY_prefix = true; }
|
|
if (prefix_src == IXCBpre) { IXCB_prefix = true; IXCB_prefetch = true; }
|
|
if (prefix_src == IYCBpre) { IYCB_prefix = true; IYCB_prefetch = true; }
|
|
|
|
FetchInstruction(FetchMemory(RegPC++));
|
|
instr_pntr = 0;
|
|
// only the first prefix in a double prefix increases R, although I don't know how / why
|
|
if (prefix_src < 4)
|
|
{
|
|
temp_R = (byte)(Regs[R] & 0x7F);
|
|
temp_R++;
|
|
temp_R &= 0x7F;
|
|
Regs[R] = (byte)((Regs[R] & 0x80) | temp_R);
|
|
}
|
|
break;
|
|
case ASGN:
|
|
ASGN_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case ADDS:
|
|
ADDS_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case EI_RETI:
|
|
// NOTE: This is needed for systems using multiple interrupt sources, it triggers the next interrupt
|
|
// Not currently implemented here
|
|
iff1 = iff2;
|
|
break;
|
|
case EI_RETN:
|
|
iff1 = iff2;
|
|
break;
|
|
case OUT:
|
|
OUT_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case IN:
|
|
IN_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case NEG:
|
|
NEG_8_Func(cur_instr[instr_pntr++]);
|
|
break;
|
|
case INT_MODE:
|
|
interruptMode = cur_instr[instr_pntr++];
|
|
break;
|
|
case RRD:
|
|
RRD_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case RLD:
|
|
RLD_Func(cur_instr[instr_pntr++], cur_instr[instr_pntr++]);
|
|
break;
|
|
case SET_FL_LD:
|
|
SET_FL_LD_Func();
|
|
break;
|
|
case SET_FL_CP:
|
|
SET_FL_CP_Func();
|
|
break;
|
|
case SET_FL_IR:
|
|
SET_FL_IR_Func(cur_instr[instr_pntr++]);
|
|
break;
|
|
case FTCH_DB:
|
|
FTCH_DB_Func();
|
|
break;
|
|
}
|
|
totalExecutedCycles++;
|
|
}
|
|
|
|
// tracer stuff
|
|
public Action<TraceInfo> TraceCallback;
|
|
|
|
public string TraceHeader
|
|
{
|
|
get { return "Z80A: PC, machine code, mnemonic, operands, registers (AF, BC, DE, HL, IX, IY, SP, Cy), flags (CNP3H5ZS)"; }
|
|
}
|
|
|
|
public TraceInfo State(bool disassemble = true)
|
|
{
|
|
int bytes_read = 0;
|
|
|
|
string disasm = disassemble ? Disassemble(RegPC, ReadMemory, out bytes_read) : "---";
|
|
string byte_code = null;
|
|
|
|
for (ushort i = 0; i < bytes_read; i++)
|
|
{
|
|
byte_code += ReadMemory((ushort)(RegPC + i)).ToHexString(2);
|
|
if (i < (bytes_read - 1))
|
|
{
|
|
byte_code += " ";
|
|
}
|
|
}
|
|
|
|
return new TraceInfo
|
|
{
|
|
Disassembly = string.Format(
|
|
"{0:X4}: {1} {2}",
|
|
RegPC,
|
|
byte_code.PadRight(12),
|
|
disasm.PadRight(26)),
|
|
RegisterInfo = string.Format(
|
|
"AF:{0:X4} BC:{1:X4} DE:{2:X4} HL:{3:X4} IX:{4:X4} IY:{5:X4} SP:{6:X4} Cy:{7} {8}{9}{10}{11}{12}{13}{14}{15}{16}",
|
|
(Regs[A] << 8) + Regs[F],
|
|
(Regs[B] << 8) + Regs[C],
|
|
(Regs[D] << 8) + Regs[E],
|
|
(Regs[H] << 8) + Regs[L],
|
|
(Regs[Ixh] << 8) + Regs[Ixl],
|
|
(Regs[Iyh] << 8) + Regs[Iyl],
|
|
Regs[SPl] | (Regs[SPh] << 8),
|
|
TotalExecutedCycles,
|
|
FlagC ? "C" : "c",
|
|
FlagN ? "N" : "n",
|
|
FlagP ? "P" : "p",
|
|
Flag3 ? "3" : "-",
|
|
FlagH ? "H" : "h",
|
|
Flag5 ? "5" : "-",
|
|
FlagZ ? "Z" : "z",
|
|
FlagS ? "S" : "s",
|
|
FlagI ? "E" : "e")
|
|
};
|
|
}
|
|
// State Save/Load
|
|
|
|
public void SyncState(Serializer ser)
|
|
{
|
|
ser.BeginSection("Z80A");
|
|
ser.Sync("Regs", ref Regs, false);
|
|
ser.Sync("NMI", ref nonMaskableInterrupt);
|
|
ser.Sync("NMIPending", ref nonMaskableInterruptPending);
|
|
ser.Sync("IM", ref interruptMode);
|
|
ser.Sync("IFF1", ref iff1);
|
|
ser.Sync("IFF2", ref iff2);
|
|
ser.Sync("Halted", ref halted);
|
|
ser.Sync("ExecutedCycles", ref totalExecutedCycles);
|
|
ser.Sync("EI_pending", ref EI_pending);
|
|
|
|
ser.Sync("instruction_pointer", ref instr_pntr);
|
|
ser.Sync("current instruction", ref cur_instr, false);
|
|
ser.Sync("opcode", ref opcode);
|
|
ser.Sync("FlagI", ref FlagI);
|
|
|
|
ser.Sync("NO Preifx", ref NO_prefix);
|
|
ser.Sync("CB Preifx", ref CB_prefix);
|
|
ser.Sync("IX_prefix", ref IX_prefix);
|
|
ser.Sync("IY_prefix", ref IY_prefix);
|
|
ser.Sync("IXCB_prefix", ref IXCB_prefix);
|
|
ser.Sync("IYCB_prefix", ref IYCB_prefix);
|
|
ser.Sync("EXTD_prefix", ref EXTD_prefix);
|
|
ser.Sync("IXCB_prefetch", ref IXCB_prefetch);
|
|
ser.Sync("IYCB_prefetch", ref IYCB_prefetch);
|
|
ser.Sync("PF", ref PF);
|
|
|
|
ser.EndSection();
|
|
}
|
|
}
|
|
}
|