beirich
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e96912dab0
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68000: fix dumb MULS/MULU/DIVS/DIVU bug
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2011-10-27 03:06:33 +00:00 |
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beirich
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0924ad07fd
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68000: fix bug in CMP instruction >_>
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2011-10-13 02:38:23 +00:00 |
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beirich
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7cedd71729
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68000: fix bug with ADDQ.W/SUBQ.W operating on address registers
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2011-10-12 02:20:03 +00:00 |
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beirich
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5b5c7c2890
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68000: add MULU, MULS, DIVU, DIVS, MOVE to CCR
Some genesis source reorganization
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2011-10-11 03:52:44 +00:00 |
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beirich
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c787b70613
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68000: implement EORI, ROXL, ROXR. Fix bugs on ADDI.L and SUBI.L. Complete MOVA timings. Work on An/PC Indexed addressing modes.
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2011-10-09 19:15:31 +00:00 |
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beirich
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2d2bfae611
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68000: implement NEG, fix bug on ANDI.L
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2011-10-09 06:19:59 +00:00 |
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beirich
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18de3c9efc
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68000: implement AND, OR, EOR. Fix interrupt bug. Fix bug with SR register
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2011-10-08 19:57:22 +00:00 |
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beirich
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18a3f3f87a
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68000: more flags fixes, especially N flag calculation. derp. :|
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2011-10-07 05:13:15 +00:00 |
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beirich
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575a8940cb
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68000: more add/sub flags fixes
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2011-10-07 04:21:20 +00:00 |
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beirich
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f2ca21759c
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68000 timings and flags fixes, some new opcode handlers
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2011-10-07 03:04:48 +00:00 |
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beirich
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89e4c5a674
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2011-01-11 02:55:51 +00:00 |