Commit Graph

9 Commits

Author SHA1 Message Date
brandman211 7ad002d5ce IntelliHawk:
-Cleanup.
-Added "Total Executed Cycles" to the log.
-By observing the aforementioned data, I realized that the docs probably meant to say 14934 instead of 14394.
--By adjusting this...TITLE SCREEN!
--Still, there are definitely discrepancies with the log that imply that I'm far from done.
-Enabled ANDR and XOR because they were executed during the title sequence, though it's hard to tell if it should at this point.
2012-12-17 04:23:59 +00:00
brandman211 5239b4f55b -Separated the STIC and PSG memory map logic into new objects.
-Foreground / Background | Color Stack Mode
--Actually made a boolean for it (FGBG).
--Reading from a write-only STIC alias of $21 does change the STIC into Color Stack mode, but it doesn't actually read.
--Color stack mode is enabled when $21 or its alias is read and it is disabled (FGBG) when written its written, both having to occur during VBlank Period 1.
---This is what I gathered from the wiki, but I'm confused as to why it says that "The STIC stays in this mode until the program accesses location $21 again." I'm assuming this doesn't mean the mode changes on every access because then I don't understand why a read would change to a different mode than a write.
--FGBG is disabled by default. I don't think it matters.
2012-08-08 23:05:55 +00:00
brandman211 80a0f8f75b -Made Intellicart its own class.
-Separated cartridge logic into a separate ICart named Cartridge.cs.
-Made WriteMemory return a bool to match ICart.Write. It currently returns true if either the cart or the core responded.

TODO: Parse the vanilla Intellivision ROM, which will hopefully include the read / writability of the data segments. adelikat seems to think that I just need to send the bytes to $5000, but I'm not convinced.
2012-07-31 06:54:20 +00:00
brandman211 0a0763966c -Refactored of the executor / disassembler / Intellicart to use more descriptive variable names and types to clear up a lot of confusion.
-Added implementation for NOP (6 cycles of nothing).
-Made SWAP actually store the result (Still disabled).
-Added breaks to the swap / shift / rotate cases (Yikes).

Instruction disassembly:

JSRD R5, $1026
MVI@ R7, R6
JSR R5, $1A83
MVO@ R5, R6
MVO@ R0, R6
MVO@ R1, R6
MVI@ R7, R4
MVI@ R7, R0
JSR R5, $1738
MVO@ R5, R6
XORR R5, R5 <- Needs implementation.
2012-07-21 05:25:52 +00:00
brandman211 1ee1d03aea -Parsed / implemented fine addresses for the Intellicart.
-Implemented the final CRC check.

I didn't get around to implementing bank-switched ranges, but I don't think it's worth worrying about that right now considering that the Intellicart is not marked as readable at the initial PC, so something is either wrong or I need to implement more things before this will work. I think I'll put Intellicarts on hold and try to get a .int / .bin to run in the meantime.
2012-07-18 05:35:10 +00:00
brandman211 0a3a392285 -Attempted to parse out memory attributes.
--In my test case, only a few segments were set to readable and nothing else was set. 0x1000, which is where the PC is initialized to, certainly isn't in a writable page.
--Although I've read that these memory attributes affect the Intellivision and not the Intellicart, I'm pretty sure this has to be implemented in the Intellicart so that my Read/WriteCart functions can choose to respond / not respond depending on these attributes. I very well could be wrong.
-Hooked Read/WriteCart into Read/WriteMemory.
-Implemented memory attributes into Read/WriteCart.
--TODO: Bank-switching.

TODO: Fine address table and memory attribute / fine address checksums.
2012-07-17 05:32:00 +00:00
brandman211 cd5458a5e4 Fixed CRC. Passes! 2012-07-17 04:16:11 +00:00
brandman211 21558eaf11 -Made ReadMemory and WriteMemory for the Intellicart Read/WriteCart and made them return nullable values instead of passing an out value.
-Started parsing data segments.
--CRC check fails. :(
-Added .bin and .rom to the Intellivision associated file extensions in the load ROM dialog.
2012-07-16 05:52:01 +00:00
brandman211 4f9539b73c -Made Executive ROM and Graphics ROM read-only. I still haven't made the memory map accessibility limited by the VBlank Period, but I'm assuming that should come way later.
-Initialized the memory devices with a tentative size that ignores the unofficial ranges.
-Masked addresses to match those sizes (That's my understanding of what the memory map needs to do based on other examples).
-Added the ICart interface.
-Started the Intellicart parser; got far enough to know that the files I'm working with are not Intellicarts. ^_^
2012-07-15 08:38:50 +00:00