2012-11-03 06:03:58 +00:00
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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namespace BizHawk.Emulation.Computers.Commodore64
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{
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2012-11-05 16:56:58 +00:00
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public class CiaRegs
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2012-11-03 17:57:14 +00:00
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{
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2012-11-05 16:56:58 +00:00
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public bool ALARM;
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public int ALARM10;
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public int ALARMHR;
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public int ALARMMIN;
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public bool ALARMPM;
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public int ALARMSEC;
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public int[] DOR = new int[2];
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public bool IALARM;
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public bool IFLG;
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public int[] INMODE = new int[2];
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public bool IRQ;
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public bool ISP;
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public bool[] IT = new bool[2];
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public bool[] LOAD = new bool[2];
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public bool[] OUTMODE = new bool[2];
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public bool[] PBON = new bool[2];
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public int[] PR = new int[2];
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public bool[] RUNMODE = new bool[2];
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public int SDR;
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public bool SPMODE;
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public bool[] START = new bool[2];
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public int[] T = new int[2];
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public int TOD10;
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public bool TODIN;
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public int TODHR;
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public int TODMIN;
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public bool TODPM;
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public int TODSEC;
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2012-11-03 07:05:07 +00:00
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2012-11-05 16:56:58 +00:00
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private DirectionalDataPort[] ports;
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private ChipSignals signal;
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2012-11-03 07:05:07 +00:00
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2012-11-05 16:56:58 +00:00
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public CiaRegs(ChipSignals newSignal, DirectionalDataPort[] newPorts)
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2012-11-03 17:57:14 +00:00
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{
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2012-11-05 16:56:58 +00:00
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ports = newPorts;
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signal = newSignal;
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2012-11-03 06:03:58 +00:00
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2012-11-05 16:56:58 +00:00
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// power on state
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this[0x04] = 0xFF;
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this[0x05] = 0xFF;
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this[0x06] = 0xFF;
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this[0x07] = 0xFF;
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this[0x0B] = 0x01;
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2012-11-03 17:57:14 +00:00
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}
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2012-11-03 07:05:07 +00:00
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2012-11-05 16:56:58 +00:00
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public byte this[int addr]
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2012-11-03 17:57:14 +00:00
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{
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2012-11-05 16:56:58 +00:00
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get
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{
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// value of open bits
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int result = 0x00;
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2012-11-03 07:05:07 +00:00
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2012-11-05 16:56:58 +00:00
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addr &= 0x0F;
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switch (addr)
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{
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case 0x00:
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result = ports[0].Data;
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break;
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case 0x01:
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result = ports[1].Data;
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break;
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case 0x02:
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result = ports[0].Direction;
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break;
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case 0x03:
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result = ports[1].Direction;
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break;
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case 0x04:
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result = (T[0] & 0xFF);
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break;
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case 0x05:
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result = ((T[0] >> 8) & 0xFF);
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break;
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case 0x06:
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result = (T[1] & 0xFF);
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break;
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case 0x07:
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result = ((T[1] >> 8) & 0xFF);
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break;
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case 0x08:
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result |= (TOD10 & 0x0F);
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break;
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case 0x09:
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result &= 0x80;
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result |= (TODSEC & 0x7F);
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break;
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case 0x0A:
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result &= 0x80;
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result |= (TODMIN & 0x7F);
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break;
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case 0x0B:
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result &= 0x40;
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result |= ((TODHR & 0x3F) | (TODPM ? 0x80 : 0x00));
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break;
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case 0x0C:
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result = SDR;
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break;
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case 0x0D:
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result &= 0x9F;
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result |= (IT[0] ? 0x01 : 0x00);
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result |= (IT[1] ? 0x02 : 0x00);
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result |= (IALARM ? 0x04 : 0x00);
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result |= (ISP ? 0x08 : 0x00);
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result |= (IFLG ? 0x10 : 0x00);
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result |= (IRQ ? 0x80 : 0x00);
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break;
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case 0x0E:
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result = (START[0] ? 0x01 : 0x00);
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result = (PBON[0] ? 0x02 : 0x00);
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result = (OUTMODE[0] ? 0x04 : 0x00);
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result = (RUNMODE[0] ? 0x08 : 0x00);
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result = (LOAD[0] ? 0x10 : 0x00);
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result = ((INMODE[0] & 0x01) << 5);
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result = (SPMODE ? 0x40 : 0x00);
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result = (TODIN ? 0x80 : 0x00);
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break;
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case 0x0F:
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result = (START[1] ? 0x01 : 0x00);
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result = (PBON[1] ? 0x02 : 0x00);
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result = (OUTMODE[1] ? 0x04 : 0x00);
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result = (RUNMODE[1] ? 0x08 : 0x00);
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result = (LOAD[1] ? 0x10 : 0x00);
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result = ((INMODE[1] & 0x03) << 5);
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result = (ALARM ? 0x80 : 0x00);
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break;
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}
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2012-11-03 10:15:44 +00:00
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2012-11-05 16:56:58 +00:00
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return (byte)(result & 0xFF);
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}
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2012-11-03 10:15:44 +00:00
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2012-11-05 16:56:58 +00:00
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set
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2012-11-03 17:57:14 +00:00
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{
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2012-11-05 16:56:58 +00:00
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byte val = value;
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addr &= 0x0F;
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switch (addr)
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2012-11-03 17:57:14 +00:00
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{
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2012-11-05 16:56:58 +00:00
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case 0x00:
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ports[0].Data = val;
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break;
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case 0x01:
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ports[1].Data = val;
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break;
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case 0x02:
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ports[0].Direction = val;
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break;
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case 0x03:
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ports[1].Direction = val;
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break;
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case 0x04:
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T[0] &= 0xFF00;
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T[0] |= val;
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break;
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case 0x05:
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T[0] &= 0x00FF;
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T[0] |= ((int)val << 8);
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break;
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case 0x06:
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T[1] &= 0xFF00;
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T[1] |= val;
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break;
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case 0x07:
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T[1] &= 0x00FF;
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T[1] |= ((int)val << 8);
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break;
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case 0x08:
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TOD10 = val & 0x0F;
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break;
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case 0x09:
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TODSEC = val & 0x7F;
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break;
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case 0x0A:
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TODMIN = val & 0x7F;
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break;
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case 0x0B:
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val &= 0x9F;
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TODHR = val;
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TODPM = ((val & 0x80) != 0x00);
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break;
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case 0x0C:
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SDR = val;
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break;
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case 0x0D:
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IT[0] = ((val & 0x01) != 0x00);
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IT[1] = ((val & 0x02) != 0x00);
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IALARM = ((val & 0x04) != 0x00);
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ISP = ((val & 0x08) != 0x00);
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IFLG = ((val & 0x10) != 0x00);
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IRQ = ((val & 0x80) != 0x00);
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break;
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case 0x0E:
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START[0] = ((val & 0x01) != 0x00);
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PBON[0] = ((val & 0x02) != 0x00);
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OUTMODE[0] = ((val & 0x04) != 0x00);
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RUNMODE[0] = ((val & 0x08) != 0x00);
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LOAD[0] = ((val & 0x10) != 0x00);
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INMODE[0] = ((val & 0x20) >> 5);
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SPMODE = ((val & 0x40) != 0x00);
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TODIN = ((val & 0x80) != 0x00);
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break;
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case 0x0F:
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START[1] = ((val & 0x01) != 0x00);
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PBON[1] = ((val & 0x02) != 0x00);
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OUTMODE[1] = ((val & 0x04) != 0x00);
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RUNMODE[1] = ((val & 0x08) != 0x00);
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LOAD[1] = ((val & 0x10) != 0x00);
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INMODE[1] = ((val & 0x60) >> 5);
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ALARM = ((val & 0x80) != 0x00);
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break;
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2012-11-03 17:57:14 +00:00
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}
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}
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2012-11-05 16:56:58 +00:00
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}
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}
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2012-11-03 10:15:44 +00:00
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2012-11-05 16:56:58 +00:00
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public class Cia
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{
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public int intMask;
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public DirectionalDataPort[] ports;
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public CiaRegs regs;
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public ChipSignals signal;
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public Cia(ChipSignals newSignal)
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{
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signal = newSignal;
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HardReset();
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2012-11-03 17:57:14 +00:00
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}
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2012-11-03 10:15:44 +00:00
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2012-11-05 16:56:58 +00:00
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public void HardReset()
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2012-11-03 17:57:14 +00:00
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{
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2012-11-05 16:56:58 +00:00
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ports = new DirectionalDataPort[2];
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regs = new CiaRegs(signal, ports);
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}
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2012-11-03 10:15:44 +00:00
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2012-11-05 16:56:58 +00:00
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public void PerformCycle()
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{
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2012-11-03 17:57:14 +00:00
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}
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2012-11-03 06:03:58 +00:00
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2012-11-03 17:57:14 +00:00
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public byte Read(ushort addr)
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{
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2012-11-05 16:56:58 +00:00
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byte result;
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2012-11-03 06:03:58 +00:00
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2012-11-03 17:57:14 +00:00
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switch (addr)
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{
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case 0x0D:
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2012-11-05 16:56:58 +00:00
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// reading this reg clears it
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result = regs[0x0D];
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regs[0x0D] = 0x00;
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return result;
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2012-11-03 17:57:14 +00:00
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default:
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2012-11-05 16:56:58 +00:00
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return regs[addr];
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2012-11-03 17:57:14 +00:00
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}
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}
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2012-11-03 06:03:58 +00:00
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2012-11-03 17:57:14 +00:00
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public void TimerTick(int index)
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{
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}
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2012-11-03 10:15:44 +00:00
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2012-11-03 17:57:14 +00:00
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public void Write(ushort addr, byte val)
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{
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switch (addr)
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{
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2012-11-05 16:56:58 +00:00
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case 0x08:
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if (regs.ALARM)
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regs.ALARM10 = val & 0x0F;
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else
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regs[addr] = val;
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2012-11-03 17:57:14 +00:00
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break;
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2012-11-05 16:56:58 +00:00
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case 0x09:
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if (regs.ALARM)
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regs.ALARMSEC = val & 0x7F;
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else
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regs[addr] = val;
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2012-11-03 17:57:14 +00:00
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break;
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2012-11-05 16:56:58 +00:00
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case 0x0A:
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if (regs.ALARM)
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regs.ALARMMIN = val & 0x7F;
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else
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regs[addr] = val;
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2012-11-03 17:57:14 +00:00
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break;
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2012-11-05 16:56:58 +00:00
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case 0x0B:
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if (regs.ALARM)
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{
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regs.ALARMHR = val & 0x1F;
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regs.ALARMPM = ((val & 0x80) != 0x00);
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}
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else
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regs[addr] = val;
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2012-11-03 17:57:14 +00:00
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break;
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case 0x0D:
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2012-11-05 16:56:58 +00:00
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intMask &= ~val;
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if ((val & 0x80) != 0x00)
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intMask ^= val;
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2012-11-03 17:57:14 +00:00
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break;
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default:
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2012-11-05 16:56:58 +00:00
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regs[addr] = val;
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2012-11-03 17:57:14 +00:00
|
|
|
|
break;
|
|
|
|
|
}
|
2012-11-05 16:56:58 +00:00
|
|
|
|
|
2012-11-03 17:57:14 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
2012-11-03 06:03:58 +00:00
|
|
|
|
}
|