Commit Graph

6847 Commits

Author SHA1 Message Date
Triang3l ee8e71cea8 [D3D12] RT dump: Fix r# allocation 2022-03-22 21:41:44 +03:00
Triang3l 920704c71a [D3D12] RT transfer: Same front/back stencil ops 2022-03-22 21:39:06 +03:00
Triang3l 1259c9f7a2 [Vulkan] Pipeline barrier merging 2022-03-21 23:02:51 +03:00
Triang3l acc4fd6846 [Vulkan] Rectangle list geometry shader 2022-03-21 22:53:19 +03:00
Triang3l c47b874a4d Merge branch 'master' into vulkan 2022-03-21 20:57:02 +03:00
Triang3l 82c1fb87aa [App] Do all fullscreen entry logic for --fullscreen=true (fixes #1999) 2022-03-14 20:42:52 +03:00
Wunkolo c1de37f381 [x64] Remove usage of `xbyak_bin2hex.h`
C++ has had binary-literals since C++14. There is no need for these
binary enum values from xbyak.
2022-03-08 12:18:58 -06:00
Wunkolo f356cf5df8 [x64] Add `VECTOR_ROTATE_LEFT_I32` overflow-test
Edit one of the lanes in this unit-test to be larger than the width of
the element-size to ensure that this case is handled correctly.

It should only mask the lower `log2(32)=5` bits of the input, causing
`33`(`100001`) to be `1`(`000001`).
2022-03-08 12:18:58 -06:00
Wunkolo 337f0b2948 [x64] Add AVX512 optimization for `VECTOR_ROTATE_LEFT(Int32)`
`vprolvd` is an almost 1:1 analog with this opcode and can be
conditionally emitted when the host supports AVX512{F,VL}.

Altivec docs say that `vrl{bhw}` masks the lower log2(n) bits of the
element-size.

[vprold](https://www.felixcloutier.com/x86/vprold:vprolvd:vprolq:vprolvq)
modulos the shift-value by the element size in bits, which is the same
as masking the lower log2(n) bits. So `vrlw` maps exactly to `vprold`.
2022-03-08 12:18:58 -06:00
Joel Linn 7e894d10a7 [kernel] Correct status for looked up objects
- The guest will check for 0x40000000 and replace it with
  0xb7 (ERROR_ALREADY_EXISTS), which is the correct return value.
  For example, see:
  https://docs.microsoft.com/en-us/windows/win32/api/synchapi/nf-synchapi-createmutexa
2022-03-08 12:17:57 -06:00
Joel Linn 91f4954967 [kernel] Refactor uses of attribute names 2022-03-08 12:17:57 -06:00
Joel Linn 38d589d1e0 [kernel] Remove unnecessary string copy 2022-03-08 12:17:57 -06:00
Joel Linn b625ef0a38 [CI] More verbose xenia-base-tests output 2022-03-08 12:17:57 -06:00
Joel Linn b72ab7b4a4 [Base] Refactor POSIX timers, fix user-after-free
Since timer_delete does not clean up already queued signals, signal info
data needs to be retained after timer deletion and object destruction in
order to circumvent use-after-free bugs.
2022-03-08 12:17:57 -06:00
Joel Linn 257b904a5e [Base] Add DelayScheduler class
Schedule callbacks whith the only guarantee that they will not be run for
the minimum duration specified. Useful for garbage collecting POSIX
timer_create() signal info data.
2022-03-08 12:17:57 -06:00
Joel Linn e0f34b97fb [Base] Check for correct thread in HResTimer tests 2022-03-08 12:17:57 -06:00
Joel Linn fb741db2fe [Base] Fix callback threads for POSIX timers 2022-03-08 12:17:57 -06:00
Joel Linn 986dcf4f65 [Base] Check success of sync primitive creation
- Mainly use `assert`s, since failure is very rare
- Forward failure of `CreateSemaphore` to guests because it is more easy
  to trigger with invalid initial parameters.
2022-03-08 12:17:57 -06:00
Joel Linn 6bd1279fc0 [Base] Forward `handle=null` as nullptr for win 2022-03-08 12:17:57 -06:00
Joel Linn 4ea6e45e0c [Base] Remove `Sleep`s from more test cases
Timing dependencies in this tests were causing spurious test failures:
- Create and Run Thread
- Test Thread QueueUserCallback

They have been largely replaced by spin waits.
2022-03-08 12:17:57 -06:00
Joel Linn e75e0eb39c [Base] Fix `Semaphore::Create` invalid parameters 2022-03-08 12:17:57 -06:00
Joel Linn bb42829308 [Base] Fix WaitMultiple on POSIX
- Never use `cond_.notify_one()` because it may wake a thread that is
  unrelated to the signalled wait handle, resulting in a lost wake and
  possible deadlock. Wait conditions are to be checked by the threads
  themselves.
- Refactor and simplify `WaitMultiple`
2022-03-08 12:17:57 -06:00
Joel Linn ca6296089e [Base] Remove timing dependency from test
- Use atomics and spin waits to synchronize threads for tests
- Improves test stability on CI
2022-03-08 12:17:57 -06:00
Joel Linn 49efbeaca8 [Base] Add spin wait helper to threading test 2022-03-08 12:17:57 -06:00
Radosław Gliński 6b45cf8447
[Base] Match exactly when no pattern in wildcard 2022-02-17 17:38:04 -06:00
Triang3l ba28ef9717 [Win32] Declare Windows 7-11 support in the manifest 2022-02-17 20:38:52 +03:00
Joel Linn 00e7de9297 [CPU] Improve vrsqrtefp accuracy 2022-02-16 17:09:28 -06:00
Joel Linn d64848245d [CPU] Improve vrefp accuracy 2022-02-16 17:09:28 -06:00
Triang3l 294c76f7c4 [UI] Remove `virtual` from Window::IsFullscreen (tracked entirely by common code) 2022-02-16 20:37:53 +03:00
Triang3l b41fb851c6 [Vulkan] Unsupported pipeline features assertion typo fix 2022-02-15 23:05:47 +03:00
Triang3l e13c4ae90b Merge branch 'master' into vulkan 2022-02-15 23:02:43 +03:00
Triang3l 9e803ccf25 [D3D12] Pad kBlendOpMap with dummy values for all 3 bits 2022-02-15 23:02:26 +03:00
Triang3l c75e0dd19e [Vulkan] Blend and depth/stencil state, small pipeline cleanup 2022-02-15 23:00:21 +03:00
Triang3l a64264ed77 Merge branch 'master' into vulkan 2022-02-14 12:37:49 +03:00
Triang3l 74c109273c [UI] Add PerMonitor fallback to Windows dpiAwareness 2022-02-14 12:35:08 +03:00
Triang3l ec5acf1875 Merge branch 'master' into vulkan 2022-02-13 23:30:41 +03:00
Triang3l 09f6081b16 [Vulkan] Fix shader bytecode path in premake5.lua 2022-02-13 23:29:46 +03:00
Triang3l b8c9d5bb8c Merge branch 'master' into vulkan 2022-02-13 23:25:39 +03:00
Triang3l e57db52285 [UI] Enable Windows PMv2 DPI awareness accidentally kept disabled after testing 2022-02-13 23:10:19 +03:00
Triang3l 7652b321d0 [UI] Fix Windows 10 1607+ DPI function loading 2022-02-13 23:07:27 +03:00
Triang3l 7fc940422c [UI] Windows AdjustWindowRect and GetClientRect usage cleanup 2022-02-13 23:01:25 +03:00
Triang3l be5f7db3ef [D3D12] Fixed-function state cleanup 2022-02-13 21:50:00 +03:00
Triang3l 325ae443da [D3D12] Rename current_cached_pipeline_ to current_guest_pipeline_ 2022-02-13 21:21:49 +03:00
Triang3l 10ec47e1fe [GPU] Move common-face polygon offset to draw_util 2022-02-13 21:18:02 +03:00
Triang3l 8d07c79897 [GPU] Cleanup RB_COLOR_MASK and RB_DEPTHCONTROL normalization 2022-02-13 20:50:31 +03:00
Triang3l 8ca67b8aa7 [Vulkan] Expose relevant portability subset features 2022-02-13 20:19:01 +03:00
Triang3l 0590346084 [Vulkan] Add Vulkan-Headers and VMA submodules 2022-02-13 20:08:08 +03:00
Triang3l 8ccb00d03d [SPIR-V] Store vfetch_full address in a variable 2022-02-07 23:00:23 +03:00
Triang3l e447cf6ed8 Merge branch 'master' into vulkan 2022-02-07 22:22:43 +03:00
Triang3l 9b1fdac986 [UI] UI common shaders to XeSL 2022-02-06 22:48:38 +03:00