647d26c20a
[a64] Implement `OPCODE_ATOMIC_COMPARE_EXCHANGE`
2024-06-23 14:00:24 -07:00
cf6c2c2aee
[a64] Implement `OPCODE_ATOMIC_EXCHANGE`
2024-06-23 14:00:23 -07:00
d656c5b462
[a64] Implement `OPCODE_{LOAD,STORE}_LOCAL`
2024-06-23 14:00:23 -07:00
8a1e343c3b
[a64] Implement `OPCODE_MEMORY_BARRIER`
2024-06-23 14:00:23 -07:00
8836eb2892
[a64] Implement `OPCODE_MEMSET`
2024-06-23 14:00:23 -07:00
4f5c640f3c
[a64] Refactor `REV{32,64}` to `REV`
...
Let the register type determine the reverse-size
REV32 was also the wrong instruction to use.
2024-06-23 14:00:23 -07:00
2b3147b2ed
[a64] Fix `CallIndirect` return address
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Should be `GUEST_RET_ADDR` not `GUEST_CALL_RET_ADDR`.
2024-06-23 14:00:23 -07:00
8b4b713e0e
[a64] Remove redundant zero-extension during address computation
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Also changes the register to X3 by default
2024-06-23 14:00:23 -07:00
018e484d6b
[a64] Implement `OPCODE_{LOAD,STORE}_MMIO`
2024-06-23 14:00:23 -07:00
b5d55e1464
[a64] Refactor XSP to SP
2024-06-23 14:00:23 -07:00
5bff71f143
[a64] Fix emitted function prolog/epilog
2024-06-23 14:00:23 -07:00
6a5f4611e2
[a64] Update Membase and Context register
2024-06-23 14:00:23 -07:00
c428d79e18
[a64] Refactor thunk prolog/epilog
2024-06-23 14:00:23 -07:00
9ec4b68cae
[a64] Optimize Volatile/NonVolatile push/pop
2024-06-23 14:00:23 -07:00
17987ca755
[a64] Use `X4` for address-generation veneer
2024-06-23 14:00:23 -07:00
9b70ea07ef
[a64] Draft Windows-ARM64 stack unwinding data
...
Things still get weird at the thunks, but this allows for callstacks between-to-guest calls
2024-06-23 14:00:23 -07:00
a1741bf609
[a64] Pad code cache with `0x00` bytes
2024-06-23 14:00:23 -07:00
dfa5bdbafb
[a64] Fix ResolveFunctionThunk call
...
Resolving the function puts it into X0 and should be called immediately after.
We were just calling ResolveFunction on ResolveFunction recursively
2024-06-23 14:00:23 -07:00
65288d5796
[a64] Fix resetting of labels during Emplace
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On the x64 side, this is the same as the `reset()` function resetting the label-manager
2024-06-23 14:00:23 -07:00
5b8ac36aa6
[a64] Fix ResolveFunction thunk
...
Register was getting stomped over
2024-06-23 14:00:23 -07:00
725ea3d08c
[a64] Implement control sequences
...
Implements control sequences such as conditional branching, breaking, and trapping
2024-06-23 14:00:23 -07:00
8257740d21
[a64] Implement HIR Branch labeling
...
Adds support for HIR labels to create actual oaknut labels
2024-06-23 14:00:23 -07:00
e5fd3d340c
[a64] Implement `OPCODE_PACK`(SHORT)
...
Fails unit tests due to subtle rounding errors
`SHORT_4` unit-test is missing but implementation is the same as `SHORT_4`
2024-06-23 14:00:23 -07:00
3b2612bfc0
[a64] Implement `OPCODE_PACK`(FLOAT16)
...
Fails the unit tests due to subtle rounding errors
2024-06-23 14:00:23 -07:00
e62f3f31d4
[a64] Fix native vector calls
...
Arguments need to be pointers stored in X0, X1, X2, ... rather than bassed directly in Q0, Q1 etc.
There are no unit tests for these functions in particular.
2024-06-23 14:00:23 -07:00
35e8a809b1
[a64] Implement `OPCODE_VECTOR_ADD`
...
There is quite literally an instruction for each and every one of these cases.
Passes unit tests
2024-06-23 14:00:23 -07:00
584c34cbd6
[a64] Implement `OPCODE_VECTOR_MAX`
...
Passes unit tests
2024-06-23 14:00:22 -07:00
ebd1f84d25
[a64] Implement `OPCODE_VECTOR_MIN`
...
Passes unit tests
2024-06-23 14:00:22 -07:00
3ac51212a6
[a64] Implement `OPCODE_VECTOR_ROTATE_LEFT`
...
Uses the emulated fallback for now. Will have to come back to this later. Passes unit tests.
2024-06-23 14:00:22 -07:00
7feea4c60c
[a64] Implement `OPCODE_VECTOR_{SHR,SHA}`
...
Passes all unit tests
2024-06-23 14:00:22 -07:00
88ed113541
[a64] Remove volatile storing of X0/Q0
...
We dont load it back so no need to store it
2024-06-23 14:00:22 -07:00
07a4df8e2f
[a64] Implement `OPCODE_VECTOR_SHL`
...
Vector registers are passed as pointers rather than directly in the `Qn` registers. So these functions should be taking pointer-type arguments rather than vector-register types directly.
Fixes `OPCODE_VECTOR_SHL` and passes unit tests.
2024-06-23 14:00:22 -07:00
3d345d71a7
[a64] Fix overwriting of return-value registers
...
These are stomping over X0 and Q0 which is returning input argument registers as return values.
Fixes some guest-to-host calls.
2024-06-23 14:00:22 -07:00
6a0e6a9ca9
[a64] Fix indirect and external calls
2024-06-23 14:00:22 -07:00
8aa4b9372a
[a64] Fix memory address generation
2024-06-23 14:00:22 -07:00
124f684987
[a64] Fix Guest-To-Host native calls
...
These calls need to preserve and restore the `lr` register.
Unit tests all run now!
2024-06-23 14:00:22 -07:00
defb68eae2
[a64] Fix StackLayout
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Wrong register index and vector-register size
2024-06-23 14:00:22 -07:00
10cba8e166
[a64] Implement `OPCODE_{SHR,SHA}`
2024-06-23 14:00:22 -07:00
67706824c6
[a64] Implement `OPCODE_VECTOR_SHA`
2024-06-23 14:00:22 -07:00
72380bf833
[a64] Implement `OPCODE_PACK`(D3DCOLOR)
2024-06-23 14:00:22 -07:00
1b574be0e6
[a64] Implement `OPCODE_LOAD_VECTOR_SHR`
2024-06-23 14:00:22 -07:00
61feb6af74
[a64] Implement `OPCODE_LOAD_VECTOR_SHL`
2024-06-23 14:00:22 -07:00
10310d7e2f
[a64] Implement `OPCODE_INSERT`
2024-06-23 14:00:22 -07:00
652b7a1370
[a64] Implement `OPCODE_SPLAT`
2024-06-23 14:00:22 -07:00
b9571cfda0
[a64] Implement `OPCODE_EXTRACT`
2024-06-23 14:00:22 -07:00
39429aada7
[a64] Fix `BYTE_SWAP_V128`
...
This just reverses the bytes of 32-bit values, not reverse the whole vector.
2024-06-23 14:00:22 -07:00
9960ef9deb
[CPU] Implement ARM64 CPU backend
...
First pass framework that gets emitted ARM code executing.
Based on the x64 backend, implements an ARM64 JIT backend.
2024-06-23 14:00:22 -07:00
2284ed417a
[Base] Add ARM64 utility functions
...
Mostly element-accessors
2024-06-23 14:00:22 -07:00
59bc265941
[a64] Integrate `oaknut` submodule
...
Header-only library for emitting arm64v8 instructions.
Enables C++20 only for the a64 backend for now
2024-06-23 14:00:22 -07:00
ffc966c9ea
[CPU] Add ARM64 backend build target
...
Adds the new `xenia-cpu-backend-a64` build-target with linkage following the x64 backend.
2024-06-23 14:00:21 -07:00
Wunkolo