fd32c0e959
[a64] Fix 32-bit store
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You wouldn't believe how much time this bug costed me
2024-06-23 14:00:24 -07:00
2d093ae4ba
[a64] Use `offsetof` to reload membase
2024-06-23 14:00:24 -07:00
47665fddb8
[a64] Compute memory offsets as 32-bit registers
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Additionally fixes some instruction forms to use the more general `STR` instruction with an offset
2024-06-23 14:00:24 -07:00
b18f2fffff
[a64] Fix up-casting zero/sign extensions
2024-06-23 14:00:24 -07:00
c6a7270a06
[a64] Fix external function call arguments
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`x0` was loading the thunk rather than using `xip`
Fixes lots of init bugs!
2024-06-23 14:00:24 -07:00
e4d3b2a484
[a64] Increase function code size to 1MiB
2024-06-23 14:00:24 -07:00
ba924feea5
[a64] Fix immediates being too large
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These instructions need to use an extra register to generate their constants if they are too large
2024-06-23 14:00:24 -07:00
540344fd27
[a64] Fix `EmitGetCurrentThreadId` type
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16-bit word rather than 8-bit
2024-06-23 14:00:24 -07:00
906d0c6590
[a64] Remove standard prolog/epilog from thunks
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Fixes callstacks!!!!
2024-06-23 14:00:24 -07:00
49f9edbfab
[a64] Reorganize guest register allocation
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Share a somewhat similar calling convention as ARM64
2024-06-23 14:00:24 -07:00
0f9769baac
[a64] Refactor `REV{16,32}` to `REV`
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Derive the reversal-size from the register-size.
REV32 is also the wrong one to be using here since it will reverse the bytes of upper and lower 32-bit words.
2024-06-23 14:00:24 -07:00
52b259369e
[a64] Fix `ComputeMemoryAddress{Offset}` register stomp
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`W1` is a possible HIR register allocation and using W1 here was stomping over it. Don't use W1, use the provided "scratch" register.
2024-06-23 14:00:24 -07:00
647d26c20a
[a64] Implement `OPCODE_ATOMIC_COMPARE_EXCHANGE`
2024-06-23 14:00:24 -07:00
cf6c2c2aee
[a64] Implement `OPCODE_ATOMIC_EXCHANGE`
2024-06-23 14:00:23 -07:00
d656c5b462
[a64] Implement `OPCODE_{LOAD,STORE}_LOCAL`
2024-06-23 14:00:23 -07:00
8a1e343c3b
[a64] Implement `OPCODE_MEMORY_BARRIER`
2024-06-23 14:00:23 -07:00
8836eb2892
[a64] Implement `OPCODE_MEMSET`
2024-06-23 14:00:23 -07:00
4f5c640f3c
[a64] Refactor `REV{32,64}` to `REV`
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Let the register type determine the reverse-size
REV32 was also the wrong instruction to use.
2024-06-23 14:00:23 -07:00
2b3147b2ed
[a64] Fix `CallIndirect` return address
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Should be `GUEST_RET_ADDR` not `GUEST_CALL_RET_ADDR`.
2024-06-23 14:00:23 -07:00
8b4b713e0e
[a64] Remove redundant zero-extension during address computation
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Also changes the register to X3 by default
2024-06-23 14:00:23 -07:00
018e484d6b
[a64] Implement `OPCODE_{LOAD,STORE}_MMIO`
2024-06-23 14:00:23 -07:00
b5d55e1464
[a64] Refactor XSP to SP
2024-06-23 14:00:23 -07:00
5bff71f143
[a64] Fix emitted function prolog/epilog
2024-06-23 14:00:23 -07:00
6a5f4611e2
[a64] Update Membase and Context register
2024-06-23 14:00:23 -07:00
c428d79e18
[a64] Refactor thunk prolog/epilog
2024-06-23 14:00:23 -07:00
9ec4b68cae
[a64] Optimize Volatile/NonVolatile push/pop
2024-06-23 14:00:23 -07:00
17987ca755
[a64] Use `X4` for address-generation veneer
2024-06-23 14:00:23 -07:00
9b70ea07ef
[a64] Draft Windows-ARM64 stack unwinding data
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Things still get weird at the thunks, but this allows for callstacks between-to-guest calls
2024-06-23 14:00:23 -07:00
a1741bf609
[a64] Pad code cache with `0x00` bytes
2024-06-23 14:00:23 -07:00
dfa5bdbafb
[a64] Fix ResolveFunctionThunk call
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Resolving the function puts it into X0 and should be called immediately after.
We were just calling ResolveFunction on ResolveFunction recursively
2024-06-23 14:00:23 -07:00
65288d5796
[a64] Fix resetting of labels during Emplace
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On the x64 side, this is the same as the `reset()` function resetting the label-manager
2024-06-23 14:00:23 -07:00
5b8ac36aa6
[a64] Fix ResolveFunction thunk
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Register was getting stomped over
2024-06-23 14:00:23 -07:00
725ea3d08c
[a64] Implement control sequences
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Implements control sequences such as conditional branching, breaking, and trapping
2024-06-23 14:00:23 -07:00
8257740d21
[a64] Implement HIR Branch labeling
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Adds support for HIR labels to create actual oaknut labels
2024-06-23 14:00:23 -07:00
e5fd3d340c
[a64] Implement `OPCODE_PACK`(SHORT)
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Fails unit tests due to subtle rounding errors
`SHORT_4` unit-test is missing but implementation is the same as `SHORT_4`
2024-06-23 14:00:23 -07:00
3b2612bfc0
[a64] Implement `OPCODE_PACK`(FLOAT16)
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Fails the unit tests due to subtle rounding errors
2024-06-23 14:00:23 -07:00
e62f3f31d4
[a64] Fix native vector calls
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Arguments need to be pointers stored in X0, X1, X2, ... rather than bassed directly in Q0, Q1 etc.
There are no unit tests for these functions in particular.
2024-06-23 14:00:23 -07:00
35e8a809b1
[a64] Implement `OPCODE_VECTOR_ADD`
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There is quite literally an instruction for each and every one of these cases.
Passes unit tests
2024-06-23 14:00:23 -07:00
584c34cbd6
[a64] Implement `OPCODE_VECTOR_MAX`
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Passes unit tests
2024-06-23 14:00:22 -07:00
ebd1f84d25
[a64] Implement `OPCODE_VECTOR_MIN`
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Passes unit tests
2024-06-23 14:00:22 -07:00
3ac51212a6
[a64] Implement `OPCODE_VECTOR_ROTATE_LEFT`
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Uses the emulated fallback for now. Will have to come back to this later. Passes unit tests.
2024-06-23 14:00:22 -07:00
7feea4c60c
[a64] Implement `OPCODE_VECTOR_{SHR,SHA}`
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Passes all unit tests
2024-06-23 14:00:22 -07:00
88ed113541
[a64] Remove volatile storing of X0/Q0
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We dont load it back so no need to store it
2024-06-23 14:00:22 -07:00
07a4df8e2f
[a64] Implement `OPCODE_VECTOR_SHL`
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Vector registers are passed as pointers rather than directly in the `Qn` registers. So these functions should be taking pointer-type arguments rather than vector-register types directly.
Fixes `OPCODE_VECTOR_SHL` and passes unit tests.
2024-06-23 14:00:22 -07:00
3d345d71a7
[a64] Fix overwriting of return-value registers
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These are stomping over X0 and Q0 which is returning input argument registers as return values.
Fixes some guest-to-host calls.
2024-06-23 14:00:22 -07:00
6a0e6a9ca9
[a64] Fix indirect and external calls
2024-06-23 14:00:22 -07:00
8aa4b9372a
[a64] Fix memory address generation
2024-06-23 14:00:22 -07:00
124f684987
[a64] Fix Guest-To-Host native calls
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These calls need to preserve and restore the `lr` register.
Unit tests all run now!
2024-06-23 14:00:22 -07:00
defb68eae2
[a64] Fix StackLayout
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Wrong register index and vector-register size
2024-06-23 14:00:22 -07:00
10cba8e166
[a64] Implement `OPCODE_{SHR,SHA}`
2024-06-23 14:00:22 -07:00
Wunkolo