ShuriZma
/
xenia
mirror of https://github.com/xenia-project/xenia.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixing SHR constant prop and new cntlz tests.

This commit is contained in:
Ben Vanik 2015-05-12 18:59:45 -07:00
parent 48ae4b65fb
commit cbdfd09e0f
9 changed files with 80 additions and 369 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

86
libxenia.vcxproj
View File

@ -414,92 +414,6 @@
</ItemGroup> </ItemGroup>
<ItemGroup> <ItemGroup>
<None Include="src\xenia\cpu\backend\x64\x64_sequence.inl" /> <None Include="src\xenia\cpu\backend\x64\x64_sequence.inl" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_add.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_addc.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_adde.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_addic.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_addme.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_addze.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_cntlzd.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_cntlzw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_divd.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_divdu.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_divw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_divwu.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_eqv.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_fabs.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_fsel.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvexx.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvl.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvr.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvsl.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvsr.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhd.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhdu.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhwu.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulld.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulli.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_mullw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_neg.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_nor.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_ori.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_rldicl.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_rldicr.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_rlwimi.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_rlwinm.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_rlwnm.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_sld.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_slw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_srad.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_sradi.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_sraw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_srawi.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_srd.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_srw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_stvew.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_stvl.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_stvr.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_subf.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfc.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfe.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfic.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfme.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfze.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vaddshs.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vadduhm.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vcfsx.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vcmpxxfp.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vctsxs.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrghb.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrghh.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrghw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrglb.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrglh.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrglw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vperm.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpermwi128.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpkd3d128.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpkshss.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpkswss.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vrfin.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vrlimi128.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsel.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vslb.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsldoi.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vslh.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vslw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltb.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsplth.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltisb.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltish.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltisw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltw.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsubshs.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsubuhm.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vupkd3d128.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vupkhsh.bin" />
<None Include="src\xenia\cpu\frontend\test\bin\instr_vupklsh.bin" />
<None Include="src\xenia\cpu\hir\opcodes.inl" /> <None Include="src\xenia\cpu\hir\opcodes.inl" />
<None Include="src\xenia\gpu\register_table.inc" /> <None Include="src\xenia\gpu\register_table.inc" />
<None Include="src\xenia\kernel\util\export_table_post.inc" /> <None Include="src\xenia\kernel\util\export_table_post.inc" />

258
libxenia.vcxproj.filters
View File

@ -1337,264 +1337,6 @@
</ClInclude> </ClInclude>
</ItemGroup> </ItemGroup>
<ItemGroup> <ItemGroup>
<None Include="src\xenia\cpu\frontend\test\bin\instr_add.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_addc.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_adde.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_addic.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_addme.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_addze.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_cntlzd.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_cntlzw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_divd.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_divdu.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_divw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_divwu.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_eqv.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_fabs.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_fsel.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvexx.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvl.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvr.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvsl.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_lvsr.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhd.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhdu.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulhwu.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulld.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mulli.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_mullw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_neg.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_nor.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_ori.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_rldicl.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_rldicr.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_rlwimi.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_rlwinm.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_rlwnm.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_sld.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_slw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_srad.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_sradi.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_sraw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_srawi.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_srd.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_srw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_stvew.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_stvl.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_stvr.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_subf.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfc.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfe.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfic.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfme.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_subfze.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vaddshs.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vadduhm.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vcfsx.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vcmpxxfp.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vctsxs.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrghb.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrghh.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrghw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrglb.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrglh.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vmrglw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vperm.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpermwi128.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpkd3d128.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpkshss.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vpkswss.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vrfin.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vrlimi128.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsel.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vslb.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsldoi.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vslh.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vslw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltb.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsplth.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltisb.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltish.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltisw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vspltw.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsubshs.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vsubuhm.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vupkd3d128.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vupkhsh.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\frontend\test\bin\instr_vupklsh.bin">
<Filter>Resource Files</Filter>
</None>
<None Include="src\xenia\cpu\backend\x64\x64_sequence.inl"> <None Include="src\xenia\cpu\backend\x64\x64_sequence.inl">
<Filter>src\xenia\cpu\backend\x64</Filter> <Filter>src\xenia\cpu\backend\x64</Filter>
</None> </None>

BIN
src/xenia/cpu/frontend/test/bin/instr_cntlzd.bin
View File

Binary file not shown.

41
src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis
View File

@ -8,14 +8,37 @@ Disassembly of section .text:
100000: 7c a6 00 74 cntlzd r6,r5 100000: 7c a6 00 74 cntlzd r6,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_cntlzd_2>: 0000000000100008 <test_cntlzd_1_constant>:
100008: 7c a6 00 74 cntlzd r6,r5 100008: 38 a0 00 00 li r5,0
10000c: 4e 80 00 20 blr 10000c: 7c a6 00 74 cntlzd r6,r5
100010: 4e 80 00 20 blr
0000000000100010 <test_cntlzd_3>: 0000000000100014 <test_cntlzd_2>:
100010: 7c a6 00 74 cntlzd r6,r5 100014: 7c a6 00 74 cntlzd r6,r5
100014: 4e 80 00 20 blr 100018: 4e 80 00 20 blr
0000000000100018 <test_cntlzd_4>: 000000000010001c <test_cntlzd_2_constant>:
100018: 7c a6 00 74 cntlzd r6,r5 10001c: 38 a0 00 01 li r5,1
10001c: 4e 80 00 20 blr 100020: 7c a6 00 74 cntlzd r6,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_cntlzd_3>:
100028: 7c a6 00 74 cntlzd r6,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_cntlzd_3_constant>:
100030: 38 a0 00 00 li r5,0
100034: 7c a5 28 f8 not r5,r5
100038: 7c a6 00 74 cntlzd r6,r5
10003c: 4e 80 00 20 blr
0000000000100040 <test_cntlzd_4>:
100040: 7c a6 00 74 cntlzd r6,r5
100044: 4e 80 00 20 blr
0000000000100048 <test_cntlzd_4_constant>:
100048: 38 a0 00 00 li r5,0
10004c: 7c a5 28 f8 not r5,r5
100050: 78 a5 f8 42 rldicl r5,r5,63,1
100054: 7c a6 00 74 cntlzd r6,r5
100058: 4e 80 00 20 blr

10
src/xenia/cpu/frontend/test/bin/instr_cntlzd.map
View File

@ -1,4 +1,8 @@
0000000000000000 t test_cntlzd_1 0000000000000000 t test_cntlzd_1
0000000000000008 t test_cntlzd_2 0000000000000008 t test_cntlzd_1_constant
0000000000000010 t test_cntlzd_3 0000000000000014 t test_cntlzd_2
0000000000000018 t test_cntlzd_4 000000000000001c t test_cntlzd_2_constant
0000000000000028 t test_cntlzd_3
0000000000000030 t test_cntlzd_3_constant
0000000000000040 t test_cntlzd_4
0000000000000048 t test_cntlzd_4_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_cntlzw.bin
View File

Binary file not shown.

42
src/xenia/cpu/frontend/test/bin/instr_cntlzw.dis
View File

@ -8,14 +8,38 @@ Disassembly of section .text:
100000: 7c a6 00 34 cntlzw r6,r5 100000: 7c a6 00 34 cntlzw r6,r5
100004: 4e 80 00 20 blr 100004: 4e 80 00 20 blr
0000000000100008 <test_cntlzw_2>: 0000000000100008 <test_cntlzw_1_constant>:
100008: 7c a6 00 34 cntlzw r6,r5 100008: 38 a0 00 00 li r5,0
10000c: 4e 80 00 20 blr 10000c: 7c a6 00 34 cntlzw r6,r5
100010: 4e 80 00 20 blr
0000000000100010 <test_cntlzw_3>: 0000000000100014 <test_cntlzw_2>:
100010: 7c a6 00 34 cntlzw r6,r5 100014: 7c a6 00 34 cntlzw r6,r5
100014: 4e 80 00 20 blr 100018: 4e 80 00 20 blr
0000000000100018 <test_cntlzw_4>: 000000000010001c <test_cntlzw_2_constant>:
100018: 7c a6 00 34 cntlzw r6,r5 10001c: 38 a0 00 01 li r5,1
10001c: 4e 80 00 20 blr 100020: 7c a6 00 34 cntlzw r6,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_cntlzw_3>:
100028: 7c a6 00 34 cntlzw r6,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_cntlzw_3_constant>:
100030: 38 a0 00 00 li r5,0
100034: 7c a5 28 f8 not r5,r5
100038: 54 a5 00 3e rotlwi r5,r5,0
10003c: 7c a6 00 34 cntlzw r6,r5
100040: 4e 80 00 20 blr
0000000000100044 <test_cntlzw_4>:
100044: 7c a6 00 34 cntlzw r6,r5
100048: 4e 80 00 20 blr
000000000010004c <test_cntlzw_4_constant>:
10004c: 38 a0 00 00 li r5,0
100050: 7c a5 28 f8 not r5,r5
100054: 54 a5 f8 7e rlwinm r5,r5,31,1,31
100058: 7c a6 00 34 cntlzw r6,r5
10005c: 4e 80 00 20 blr

10
src/xenia/cpu/frontend/test/bin/instr_cntlzw.map
View File

@ -1,4 +1,8 @@
0000000000000000 t test_cntlzw_1 0000000000000000 t test_cntlzw_1
0000000000000008 t test_cntlzw_2 0000000000000008 t test_cntlzw_1_constant
0000000000000010 t test_cntlzw_3 0000000000000014 t test_cntlzw_2
0000000000000018 t test_cntlzw_4 000000000000001c t test_cntlzw_2_constant
0000000000000028 t test_cntlzw_3
0000000000000030 t test_cntlzw_3_constant
0000000000000044 t test_cntlzw_4
000000000000004c t test_cntlzw_4_constant

2
src/xenia/cpu/hir/value.cc
View File

@ -552,7 +552,7 @@ void Value::Shr(Value* other) {
constant.i32 = (uint32_t)constant.i32 >> other->constant.i8; constant.i32 = (uint32_t)constant.i32 >> other->constant.i8;
break; break;
case INT64_TYPE: case INT64_TYPE:
constant.i64 = (uint16_t)constant.i64 >> other->constant.i8; constant.i64 = (uint64_t)constant.i64 >> other->constant.i8;
break; break;
default: default:
assert_unhandled_case(type); assert_unhandled_case(type);