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Fixing adde_constant.

This commit is contained in:
Ben Vanik 2015-05-12 22:53:20 -07:00
parent dda6f3b6bd
commit 91c6ad8715
8 changed files with 193 additions and 78 deletions
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16
src/xenia/cpu/backend/x64/x64_sequence.inl
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@ -574,7 +574,20 @@ struct SingleSequence : public Sequence<SingleSequence<SEQ, T>, T> {
const REG_REG_FN& reg_reg_fn,
const REG_CONST_FN& reg_const_fn) {
if (i.src1.is_constant) {
assert_true(!i.src2.is_constant);
if (i.src2.is_constant) {
if (i.src1.ConstantFitsIn32Reg()) {
e.mov(i.dest, i.src2.constant());
reg_const_fn(e, i.dest, static_cast<int32_t>(i.src1.constant()));
} else if (i.src2.ConstantFitsIn32Reg()) {
e.mov(i.dest, i.src1.constant());
reg_const_fn(e, i.dest, static_cast<int32_t>(i.src2.constant()));
} else {
e.mov(i.dest, i.src1.constant());
auto temp = GetTempReg<typename decltype(i.src2)::reg_type>(e);
e.mov(temp, i.src2.constant());
reg_reg_fn(e, i.dest, temp);
}
} else {
if (i.dest == i.src2) {
if (i.src1.ConstantFitsIn32Reg()) {
reg_const_fn(e, i.dest, static_cast<int32_t>(i.src1.constant()));
@ -587,6 +600,7 @@ struct SingleSequence : public Sequence<SingleSequence<SEQ, T>, T> {
e.mov(i.dest, i.src1.constant());
reg_reg_fn(e, i.dest, i.src2);
}
}
} else if (i.src2.is_constant) {
if (i.dest == i.src1) {
if (i.src2.ConstantFitsIn32Reg()) {

10
src/xenia/cpu/backend/x64/x64_sequences.cc
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@ -2702,22 +2702,12 @@ void EmitAddCarryXX(X64Emitter& e, const ARGS& i) {
}
e.sahf();
}
if (i.src1.is_constant && i.src2.is_constant) {
auto ab = i.src1.constant() + i.src2.constant();
if (!ab) {
e.xor(i.dest, i.dest);
} else {
e.mov(i.dest, ab);
}
e.adc(i.dest, 0);
} else {
SEQ::EmitCommutativeBinaryOp(
e, i, [](X64Emitter& e, const REG& dest_src, const REG& src) {
e.adc(dest_src, src);
}, [](X64Emitter& e, const REG& dest_src, int32_t constant) {
e.adc(dest_src, constant);
});
}
if (i.instr->flags & ARITHMETIC_SET_CARRY) {
// CF is set if carried.
e.StoreEflags();

BIN
src/xenia/cpu/frontend/test/bin/instr_add.bin
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Binary file not shown.

20
src/xenia/cpu/frontend/test/bin/instr_add.dis
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@ -4,6 +4,20 @@ Disassembly of section .text:
100000: 7d 65 ca 14 add r11,r5,r25
100004: 4e 80 00 20 blr
0000000000100008 <test_add_2>:
100008: 7d 60 ca 14 add r11,r0,r25
10000c: 4e 80 00 20 blr
0000000000100008 <test_add_1_constant>:
100008: 3c a0 00 10 lis r5,16
10000c: 3b 20 ff ff li r25,-1
100010: 7b 39 04 20 clrldi r25,r25,48
100014: 7d 65 ca 14 add r11,r5,r25
100018: 4e 80 00 20 blr
000000000010001c <test_add_2>:
10001c: 7d 60 ca 14 add r11,r0,r25
100020: 4e 80 00 20 blr
0000000000100024 <test_add_2_constant>:
100024: 3c 00 00 10 lis r0,16
100028: 3b 20 ff ff li r25,-1
10002c: 7b 39 04 20 clrldi r25,r25,48
100030: 7d 60 ca 14 add r11,r0,r25
100034: 4e 80 00 20 blr

4
src/xenia/cpu/frontend/test/bin/instr_add.map
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@ -1,2 +1,4 @@
0000000000000000 t test_add_1
0000000000000008 t test_add_2
0000000000000008 t test_add_1_constant
000000000000001c t test_add_2
0000000000000024 t test_add_2_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_adde.bin
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Binary file not shown.

171
src/xenia/cpu/frontend/test/bin/instr_adde.dis
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@ -5,46 +5,44 @@ Disassembly of section .text:
100004: 7c c0 01 14 adde r6,r0,r0
100008: 4e 80 00 20 blr
000000000010000c <test_adde_2>:
10000c: 7c 63 1a 78 xor r3,r3,r3
100010: 7c 63 18 f8 not r3,r3
100014: 30 63 00 01 addic r3,r3,1
100018: 7c 64 29 14 adde r3,r4,r5
10001c: 7c c0 01 14 adde r6,r0,r0
100020: 4e 80 00 20 blr
000000000010000c <test_adde_1_constant>:
10000c: 38 80 00 01 li r4,1
100010: 38 a0 00 02 li r5,2
100014: 7c 64 29 14 adde r3,r4,r5
100018: 7c c0 01 14 adde r6,r0,r0
10001c: 4e 80 00 20 blr
0000000000100024 <test_adde_3>:
100024: 7c 64 29 14 adde r3,r4,r5
100028: 7c c0 01 14 adde r6,r0,r0
10002c: 4e 80 00 20 blr
0000000000100020 <test_adde_2>:
100020: 7c 63 1a 78 xor r3,r3,r3
100024: 7c 63 18 f8 not r3,r3
100028: 30 63 00 01 addic r3,r3,1
10002c: 7c 64 29 14 adde r3,r4,r5
100030: 7c c0 01 14 adde r6,r0,r0
100034: 4e 80 00 20 blr
0000000000100030 <test_adde_4>:
100030: 7c 63 1a 78 xor r3,r3,r3
100034: 7c 63 18 f8 not r3,r3
100038: 30 63 00 01 addic r3,r3,1
10003c: 7c 64 29 14 adde r3,r4,r5
100040: 7c c0 01 14 adde r6,r0,r0
100044: 4e 80 00 20 blr
0000000000100038 <test_adde_2_constant>:
100038: 38 80 00 01 li r4,1
10003c: 38 a0 00 02 li r5,2
100040: 7c 63 1a 78 xor r3,r3,r3
100044: 7c 63 18 f8 not r3,r3
100048: 30 63 00 01 addic r3,r3,1
10004c: 7c 64 29 14 adde r3,r4,r5
100050: 7c c0 01 14 adde r6,r0,r0
100054: 4e 80 00 20 blr
0000000000100048 <test_adde_5>:
100048: 7c 64 29 14 adde r3,r4,r5
10004c: 7c c0 01 14 adde r6,r0,r0
100050: 4e 80 00 20 blr
0000000000100058 <test_adde_3>:
100058: 7c 64 29 14 adde r3,r4,r5
10005c: 7c c0 01 14 adde r6,r0,r0
100060: 4e 80 00 20 blr
0000000000100054 <test_adde_6>:
100054: 7c 63 1a 78 xor r3,r3,r3
100058: 7c 63 18 f8 not r3,r3
10005c: 30 63 00 01 addic r3,r3,1
100060: 7c 64 29 14 adde r3,r4,r5
100064: 7c c0 01 14 adde r6,r0,r0
100068: 4e 80 00 20 blr
000000000010006c <test_adde_7>:
0000000000100064 <test_adde_3_constant>:
100064: 38 80 ff ff li r4,-1
100068: 38 a0 00 00 li r5,0
10006c: 7c 64 29 14 adde r3,r4,r5
100070: 7c c0 01 14 adde r6,r0,r0
100074: 4e 80 00 20 blr
0000000000100078 <test_adde_8>:
0000000000100078 <test_adde_4>:
100078: 7c 63 1a 78 xor r3,r3,r3
10007c: 7c 63 18 f8 not r3,r3
100080: 30 63 00 01 addic r3,r3,1
@ -52,15 +50,102 @@ Disassembly of section .text:
100088: 7c c0 01 14 adde r6,r0,r0
10008c: 4e 80 00 20 blr
0000000000100090 <test_adde_9>:
100090: 7c 64 29 14 adde r3,r4,r5
100094: 7c c0 01 14 adde r6,r0,r0
100098: 4e 80 00 20 blr
0000000000100090 <test_adde_4_constant>:
100090: 38 80 ff ff li r4,-1
100094: 38 a0 00 00 li r5,0
100098: 7c 63 1a 78 xor r3,r3,r3
10009c: 7c 63 18 f8 not r3,r3
1000a0: 30 63 00 01 addic r3,r3,1
1000a4: 7c 64 29 14 adde r3,r4,r5
1000a8: 7c c0 01 14 adde r6,r0,r0
1000ac: 4e 80 00 20 blr
000000000010009c <test_adde_10>:
10009c: 7c 63 1a 78 xor r3,r3,r3
1000a0: 7c 63 18 f8 not r3,r3
1000a4: 30 63 00 01 addic r3,r3,1
1000a8: 7c 64 29 14 adde r3,r4,r5
1000ac: 7c c0 01 14 adde r6,r0,r0
1000b0: 4e 80 00 20 blr
00000000001000b0 <test_adde_5>:
1000b0: 7c 64 29 14 adde r3,r4,r5
1000b4: 7c c0 01 14 adde r6,r0,r0
1000b8: 4e 80 00 20 blr
00000000001000bc <test_adde_5_constant>:
1000bc: 38 80 ff ff li r4,-1
1000c0: 38 a0 00 01 li r5,1
1000c4: 7c 64 29 14 adde r3,r4,r5
1000c8: 7c c0 01 14 adde r6,r0,r0
1000cc: 4e 80 00 20 blr
00000000001000d0 <test_adde_6>:
1000d0: 7c 63 1a 78 xor r3,r3,r3
1000d4: 7c 63 18 f8 not r3,r3
1000d8: 30 63 00 01 addic r3,r3,1
1000dc: 7c 64 29 14 adde r3,r4,r5
1000e0: 7c c0 01 14 adde r6,r0,r0
1000e4: 4e 80 00 20 blr
00000000001000e8 <test_adde_6_constant>:
1000e8: 38 80 ff ff li r4,-1
1000ec: 38 a0 00 01 li r5,1
1000f0: 7c 63 1a 78 xor r3,r3,r3
1000f4: 7c 63 18 f8 not r3,r3
1000f8: 30 63 00 01 addic r3,r3,1
1000fc: 7c 64 29 14 adde r3,r4,r5
100100: 7c c0 01 14 adde r6,r0,r0
100104: 4e 80 00 20 blr
0000000000100108 <test_adde_7>:
100108: 7c 64 29 14 adde r3,r4,r5
10010c: 7c c0 01 14 adde r6,r0,r0
100110: 4e 80 00 20 blr
0000000000100114 <test_adde_7_constant>:
100114: 38 80 ff ff li r4,-1
100118: 38 a0 00 7b li r5,123
10011c: 7c 64 29 14 adde r3,r4,r5
100120: 7c c0 01 14 adde r6,r0,r0
100124: 4e 80 00 20 blr
0000000000100128 <test_adde_8>:
100128: 7c 63 1a 78 xor r3,r3,r3
10012c: 7c 63 18 f8 not r3,r3
100130: 30 63 00 01 addic r3,r3,1
100134: 7c 64 29 14 adde r3,r4,r5
100138: 7c c0 01 14 adde r6,r0,r0
10013c: 4e 80 00 20 blr
0000000000100140 <test_adde_8_constant>:
100140: 38 80 ff ff li r4,-1
100144: 38 a0 00 7b li r5,123
100148: 7c 63 1a 78 xor r3,r3,r3
10014c: 7c 63 18 f8 not r3,r3
100150: 30 63 00 01 addic r3,r3,1
100154: 7c 64 29 14 adde r3,r4,r5
100158: 7c c0 01 14 adde r6,r0,r0
10015c: 4e 80 00 20 blr
0000000000100160 <test_adde_9>:
100160: 7c 64 29 14 adde r3,r4,r5
100164: 7c c0 01 14 adde r6,r0,r0
100168: 4e 80 00 20 blr
000000000010016c <test_adde_9_constant>:
10016c: 38 a0 ff ff li r5,-1
100170: 78 a4 f8 42 rldicl r4,r5,63,1
100174: 7c 64 29 14 adde r3,r4,r5
100178: 7c c0 01 14 adde r6,r0,r0
10017c: 4e 80 00 20 blr
0000000000100180 <test_adde_10>:
100180: 7c 63 1a 78 xor r3,r3,r3
100184: 7c 63 18 f8 not r3,r3
100188: 30 63 00 01 addic r3,r3,1
10018c: 7c 64 29 14 adde r3,r4,r5
100190: 7c c0 01 14 adde r6,r0,r0
100194: 4e 80 00 20 blr
0000000000100198 <test_adde_10_constant>:
100198: 38 a0 ff ff li r5,-1
10019c: 78 a4 f8 42 rldicl r4,r5,63,1
1001a0: 7c 63 1a 78 xor r3,r3,r3
1001a4: 7c 63 18 f8 not r3,r3
1001a8: 30 63 00 01 addic r3,r3,1
1001ac: 7c 64 29 14 adde r3,r4,r5
1001b0: 7c c0 01 14 adde r6,r0,r0
1001b4: 4e 80 00 20 blr

28
src/xenia/cpu/frontend/test/bin/instr_adde.map
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@ -1,10 +1,20 @@
0000000000000000 t test_adde_1
000000000000000c t test_adde_2
0000000000000024 t test_adde_3
0000000000000030 t test_adde_4
0000000000000048 t test_adde_5
0000000000000054 t test_adde_6
000000000000006c t test_adde_7
0000000000000078 t test_adde_8
0000000000000090 t test_adde_9
000000000000009c t test_adde_10
000000000000000c t test_adde_1_constant
0000000000000020 t test_adde_2
0000000000000038 t test_adde_2_constant
0000000000000058 t test_adde_3
0000000000000064 t test_adde_3_constant
0000000000000078 t test_adde_4
0000000000000090 t test_adde_4_constant
00000000000000b0 t test_adde_5
00000000000000bc t test_adde_5_constant
00000000000000d0 t test_adde_6
00000000000000e8 t test_adde_6_constant
0000000000000108 t test_adde_7
0000000000000114 t test_adde_7_constant
0000000000000128 t test_adde_8
0000000000000140 t test_adde_8_constant
0000000000000160 t test_adde_9
000000000000016c t test_adde_9_constant
0000000000000180 t test_adde_10
0000000000000198 t test_adde_10_constant