From 91c6ad8715dc09598e391800fa9214e144427564 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Tue, 12 May 2015 22:53:20 -0700 Subject: [PATCH] Fixing adde_constant. --- src/xenia/cpu/backend/x64/x64_sequence.inl | 26 ++- src/xenia/cpu/backend/x64/x64_sequences.cc | 22 +-- src/xenia/cpu/frontend/test/bin/instr_add.bin | Bin 16 -> 56 bytes src/xenia/cpu/frontend/test/bin/instr_add.dis | 20 +- src/xenia/cpu/frontend/test/bin/instr_add.map | 4 +- .../cpu/frontend/test/bin/instr_adde.bin | Bin 180 -> 440 bytes .../cpu/frontend/test/bin/instr_adde.dis | 171 +++++++++++++----- .../cpu/frontend/test/bin/instr_adde.map | 28 ++- 8 files changed, 193 insertions(+), 78 deletions(-) diff --git a/src/xenia/cpu/backend/x64/x64_sequence.inl b/src/xenia/cpu/backend/x64/x64_sequence.inl index 77ce8ca1b..b155b8dae 100644 --- a/src/xenia/cpu/backend/x64/x64_sequence.inl +++ b/src/xenia/cpu/backend/x64/x64_sequence.inl @@ -574,18 +574,32 @@ struct SingleSequence : public Sequence, T> { const REG_REG_FN& reg_reg_fn, const REG_CONST_FN& reg_const_fn) { if (i.src1.is_constant) { - assert_true(!i.src2.is_constant); - if (i.dest == i.src2) { + if (i.src2.is_constant) { if (i.src1.ConstantFitsIn32Reg()) { + e.mov(i.dest, i.src2.constant()); reg_const_fn(e, i.dest, static_cast(i.src1.constant())); + } else if (i.src2.ConstantFitsIn32Reg()) { + e.mov(i.dest, i.src1.constant()); + reg_const_fn(e, i.dest, static_cast(i.src2.constant())); } else { - auto temp = GetTempReg(e); - e.mov(temp, i.src1.constant()); + e.mov(i.dest, i.src1.constant()); + auto temp = GetTempReg(e); + e.mov(temp, i.src2.constant()); reg_reg_fn(e, i.dest, temp); } } else { - e.mov(i.dest, i.src1.constant()); - reg_reg_fn(e, i.dest, i.src2); + if (i.dest == i.src2) { + if (i.src1.ConstantFitsIn32Reg()) { + reg_const_fn(e, i.dest, static_cast(i.src1.constant())); + } else { + auto temp = GetTempReg(e); + e.mov(temp, i.src1.constant()); + reg_reg_fn(e, i.dest, temp); + } + } else { + e.mov(i.dest, i.src1.constant()); + reg_reg_fn(e, i.dest, i.src2); + } } } else if (i.src2.is_constant) { if (i.dest == i.src1) { diff --git a/src/xenia/cpu/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc index f02fb51db..a6b78feb5 100644 --- a/src/xenia/cpu/backend/x64/x64_sequences.cc +++ b/src/xenia/cpu/backend/x64/x64_sequences.cc @@ -2702,22 +2702,12 @@ void EmitAddCarryXX(X64Emitter& e, const ARGS& i) { } e.sahf(); } - if (i.src1.is_constant && i.src2.is_constant) { - auto ab = i.src1.constant() + i.src2.constant(); - if (!ab) { - e.xor(i.dest, i.dest); - } else { - e.mov(i.dest, ab); - } - e.adc(i.dest, 0); - } else { - SEQ::EmitCommutativeBinaryOp( - e, i, [](X64Emitter& e, const REG& dest_src, const REG& src) { - e.adc(dest_src, src); - }, [](X64Emitter& e, const REG& dest_src, int32_t constant) { - e.adc(dest_src, constant); - }); - } + SEQ::EmitCommutativeBinaryOp( + e, i, [](X64Emitter& e, const REG& dest_src, const REG& src) { + e.adc(dest_src, src); + }, [](X64Emitter& e, const REG& dest_src, int32_t constant) { + e.adc(dest_src, constant); + }); if (i.instr->flags & ARITHMETIC_SET_CARRY) { // CF is set if carried. e.StoreEflags(); diff --git a/src/xenia/cpu/frontend/test/bin/instr_add.bin b/src/xenia/cpu/frontend/test/bin/instr_add.bin index d5b186a6559ed3fce8053fbbc796cb15eec58b25..ceb82a07180de9fcc60b970a3b7bb25f84b37a27 100644 GIT binary patch literal 56 ncmb: - 100008: 7d 60 ca 14 add r11,r0,r25 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 3c a0 00 10 lis r5,16 + 10000c: 3b 20 ff ff li r25,-1 + 100010: 7b 39 04 20 clrldi r25,r25,48 + 100014: 7d 65 ca 14 add r11,r5,r25 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 7d 60 ca 14 add r11,r0,r25 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 3c 00 00 10 lis r0,16 + 100028: 3b 20 ff ff li r25,-1 + 10002c: 7b 39 04 20 clrldi r25,r25,48 + 100030: 7d 60 ca 14 add r11,r0,r25 + 100034: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_add.map b/src/xenia/cpu/frontend/test/bin/instr_add.map index 3da0d3b75..9bc31b7e2 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_add.map +++ b/src/xenia/cpu/frontend/test/bin/instr_add.map @@ -1,2 +1,4 @@ 0000000000000000 t test_add_1 -0000000000000008 t test_add_2 +0000000000000008 t test_add_1_constant +000000000000001c t test_add_2 +0000000000000024 t test_add_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_adde.bin b/src/xenia/cpu/frontend/test/bin/instr_adde.bin index 3b467563d788d9f2a8accb729255d78788dd7526..464ddfe7df7976a47a8976080dca6f16d5e7120a 100644 GIT binary patch literal 440 zcmb-51JI6x delta 31 WcmdnNyoGUMj>^OhJQFJ: - 10000c: 7c 63 1a 78 xor r3,r3,r3 - 100010: 7c 63 18 f8 not r3,r3 - 100014: 30 63 00 01 addic r3,r3,1 - 100018: 7c 64 29 14 adde r3,r4,r5 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 38 a0 00 02 li r5,2 + 100014: 7c 64 29 14 adde r3,r4,r5 + 100018: 7c c0 01 14 adde r6,r0,r0 + 10001c: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 64 29 14 adde r3,r4,r5 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100020 : + 100020: 7c 63 1a 78 xor r3,r3,r3 + 100024: 7c 63 18 f8 not r3,r3 + 100028: 30 63 00 01 addic r3,r3,1 + 10002c: 7c 64 29 14 adde r3,r4,r5 + 100030: 7c c0 01 14 adde r6,r0,r0 + 100034: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 63 1a 78 xor r3,r3,r3 - 100034: 7c 63 18 f8 not r3,r3 - 100038: 30 63 00 01 addic r3,r3,1 - 10003c: 7c 64 29 14 adde r3,r4,r5 - 100040: 7c c0 01 14 adde r6,r0,r0 - 100044: 4e 80 00 20 blr +0000000000100038 : + 100038: 38 80 00 01 li r4,1 + 10003c: 38 a0 00 02 li r5,2 + 100040: 7c 63 1a 78 xor r3,r3,r3 + 100044: 7c 63 18 f8 not r3,r3 + 100048: 30 63 00 01 addic r3,r3,1 + 10004c: 7c 64 29 14 adde r3,r4,r5 + 100050: 7c c0 01 14 adde r6,r0,r0 + 100054: 4e 80 00 20 blr -0000000000100048 : - 100048: 7c 64 29 14 adde r3,r4,r5 - 10004c: 7c c0 01 14 adde r6,r0,r0 - 100050: 4e 80 00 20 blr +0000000000100058 : + 100058: 7c 64 29 14 adde r3,r4,r5 + 10005c: 7c c0 01 14 adde r6,r0,r0 + 100060: 4e 80 00 20 blr -0000000000100054 : - 100054: 7c 63 1a 78 xor r3,r3,r3 - 100058: 7c 63 18 f8 not r3,r3 - 10005c: 30 63 00 01 addic r3,r3,1 - 100060: 7c 64 29 14 adde r3,r4,r5 - 100064: 7c c0 01 14 adde r6,r0,r0 - 100068: 4e 80 00 20 blr - -000000000010006c : +0000000000100064 : + 100064: 38 80 ff ff li r4,-1 + 100068: 38 a0 00 00 li r5,0 10006c: 7c 64 29 14 adde r3,r4,r5 100070: 7c c0 01 14 adde r6,r0,r0 100074: 4e 80 00 20 blr -0000000000100078 : +0000000000100078 : 100078: 7c 63 1a 78 xor r3,r3,r3 10007c: 7c 63 18 f8 not r3,r3 100080: 30 63 00 01 addic r3,r3,1 @@ -52,15 +50,102 @@ Disassembly of section .text: 100088: 7c c0 01 14 adde r6,r0,r0 10008c: 4e 80 00 20 blr -0000000000100090 : - 100090: 7c 64 29 14 adde r3,r4,r5 - 100094: 7c c0 01 14 adde r6,r0,r0 - 100098: 4e 80 00 20 blr +0000000000100090 : + 100090: 38 80 ff ff li r4,-1 + 100094: 38 a0 00 00 li r5,0 + 100098: 7c 63 1a 78 xor r3,r3,r3 + 10009c: 7c 63 18 f8 not r3,r3 + 1000a0: 30 63 00 01 addic r3,r3,1 + 1000a4: 7c 64 29 14 adde r3,r4,r5 + 1000a8: 7c c0 01 14 adde r6,r0,r0 + 1000ac: 4e 80 00 20 blr -000000000010009c : - 10009c: 7c 63 1a 78 xor r3,r3,r3 - 1000a0: 7c 63 18 f8 not r3,r3 - 1000a4: 30 63 00 01 addic r3,r3,1 - 1000a8: 7c 64 29 14 adde r3,r4,r5 - 1000ac: 7c c0 01 14 adde r6,r0,r0 - 1000b0: 4e 80 00 20 blr +00000000001000b0 : + 1000b0: 7c 64 29 14 adde r3,r4,r5 + 1000b4: 7c c0 01 14 adde r6,r0,r0 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 38 80 ff ff li r4,-1 + 1000c0: 38 a0 00 01 li r5,1 + 1000c4: 7c 64 29 14 adde r3,r4,r5 + 1000c8: 7c c0 01 14 adde r6,r0,r0 + 1000cc: 4e 80 00 20 blr + +00000000001000d0 : + 1000d0: 7c 63 1a 78 xor r3,r3,r3 + 1000d4: 7c 63 18 f8 not r3,r3 + 1000d8: 30 63 00 01 addic r3,r3,1 + 1000dc: 7c 64 29 14 adde r3,r4,r5 + 1000e0: 7c c0 01 14 adde r6,r0,r0 + 1000e4: 4e 80 00 20 blr + +00000000001000e8 : + 1000e8: 38 80 ff ff li r4,-1 + 1000ec: 38 a0 00 01 li r5,1 + 1000f0: 7c 63 1a 78 xor r3,r3,r3 + 1000f4: 7c 63 18 f8 not r3,r3 + 1000f8: 30 63 00 01 addic r3,r3,1 + 1000fc: 7c 64 29 14 adde r3,r4,r5 + 100100: 7c c0 01 14 adde r6,r0,r0 + 100104: 4e 80 00 20 blr + +0000000000100108 : + 100108: 7c 64 29 14 adde r3,r4,r5 + 10010c: 7c c0 01 14 adde r6,r0,r0 + 100110: 4e 80 00 20 blr + +0000000000100114 : + 100114: 38 80 ff ff li r4,-1 + 100118: 38 a0 00 7b li r5,123 + 10011c: 7c 64 29 14 adde r3,r4,r5 + 100120: 7c c0 01 14 adde r6,r0,r0 + 100124: 4e 80 00 20 blr + +0000000000100128 : + 100128: 7c 63 1a 78 xor r3,r3,r3 + 10012c: 7c 63 18 f8 not r3,r3 + 100130: 30 63 00 01 addic r3,r3,1 + 100134: 7c 64 29 14 adde r3,r4,r5 + 100138: 7c c0 01 14 adde r6,r0,r0 + 10013c: 4e 80 00 20 blr + +0000000000100140 : + 100140: 38 80 ff ff li r4,-1 + 100144: 38 a0 00 7b li r5,123 + 100148: 7c 63 1a 78 xor r3,r3,r3 + 10014c: 7c 63 18 f8 not r3,r3 + 100150: 30 63 00 01 addic r3,r3,1 + 100154: 7c 64 29 14 adde r3,r4,r5 + 100158: 7c c0 01 14 adde r6,r0,r0 + 10015c: 4e 80 00 20 blr + +0000000000100160 : + 100160: 7c 64 29 14 adde r3,r4,r5 + 100164: 7c c0 01 14 adde r6,r0,r0 + 100168: 4e 80 00 20 blr + +000000000010016c : + 10016c: 38 a0 ff ff li r5,-1 + 100170: 78 a4 f8 42 rldicl r4,r5,63,1 + 100174: 7c 64 29 14 adde r3,r4,r5 + 100178: 7c c0 01 14 adde r6,r0,r0 + 10017c: 4e 80 00 20 blr + +0000000000100180 : + 100180: 7c 63 1a 78 xor r3,r3,r3 + 100184: 7c 63 18 f8 not r3,r3 + 100188: 30 63 00 01 addic r3,r3,1 + 10018c: 7c 64 29 14 adde r3,r4,r5 + 100190: 7c c0 01 14 adde r6,r0,r0 + 100194: 4e 80 00 20 blr + +0000000000100198 : + 100198: 38 a0 ff ff li r5,-1 + 10019c: 78 a4 f8 42 rldicl r4,r5,63,1 + 1001a0: 7c 63 1a 78 xor r3,r3,r3 + 1001a4: 7c 63 18 f8 not r3,r3 + 1001a8: 30 63 00 01 addic r3,r3,1 + 1001ac: 7c 64 29 14 adde r3,r4,r5 + 1001b0: 7c c0 01 14 adde r6,r0,r0 + 1001b4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_adde.map b/src/xenia/cpu/frontend/test/bin/instr_adde.map index aa560c21a..a48a1116d 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_adde.map +++ b/src/xenia/cpu/frontend/test/bin/instr_adde.map @@ -1,10 +1,20 @@ 0000000000000000 t test_adde_1 -000000000000000c t test_adde_2 -0000000000000024 t test_adde_3 -0000000000000030 t test_adde_4 -0000000000000048 t test_adde_5 -0000000000000054 t test_adde_6 -000000000000006c t test_adde_7 -0000000000000078 t test_adde_8 -0000000000000090 t test_adde_9 -000000000000009c t test_adde_10 +000000000000000c t test_adde_1_constant +0000000000000020 t test_adde_2 +0000000000000038 t test_adde_2_constant +0000000000000058 t test_adde_3 +0000000000000064 t test_adde_3_constant +0000000000000078 t test_adde_4 +0000000000000090 t test_adde_4_constant +00000000000000b0 t test_adde_5 +00000000000000bc t test_adde_5_constant +00000000000000d0 t test_adde_6 +00000000000000e8 t test_adde_6_constant +0000000000000108 t test_adde_7 +0000000000000114 t test_adde_7_constant +0000000000000128 t test_adde_8 +0000000000000140 t test_adde_8_constant +0000000000000160 t test_adde_9 +000000000000016c t test_adde_9_constant +0000000000000180 t test_adde_10 +0000000000000198 t test_adde_10_constant