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Tests for and.

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gibbed 2015-05-14 01:56:30 -05:00
parent 30f4556baf
commit 5ec6b7973b
1 changed files with 205 additions and 0 deletions
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src/xenia/cpu/frontend/test/instr_and.s Normal file
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test_and_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_and_1_constant:
li r5, -1
li r25, -1
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
test_and_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
test_and_2_constant:
li r5, -1
li r25, 0
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
test_and_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_and_3_constant:
li r5, 0
li r25, -1
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
test_and_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
test_and_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
and r11, r5, r25
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
test_and_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
and r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
test_and_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
and r11, r0, r25
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
test_and_cr_1:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_and_cr_1_constant:
li r5, -1
li r25, -1
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r12 0x80000000
test_and_cr_2:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_2_constant:
li r5, -1
li r25, 0
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_3:
#_ REGISTER_IN r5 0
#_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_3_constant:
li r5, 0
li r25, -1
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0
#_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r11 0
#_ REGISTER_OUT r12 0x20000000
test_and_cr_4:
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r25 0x0000FFFF
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
#_ REGISTER_OUT r12 0x40000000
test_and_cr_4_constant:
li r5, -1
li r25, -1
clrldi r25, r25, 48
and. r11, r5, r25
mfcr r12
blr
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x0000FFFF
#_ REGISTER_OUT r12 0x40000000
test_and_cr_5:
#_ REGISTER_IN r0 0x100000FF
#_ REGISTER_IN r25 0x0000FFFF
and. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
#_ REGISTER_OUT r12 0x40000000
test_and_cr_5_constant:
lis r0, 0x1000
ori r0, r0, 0xFF
li r25, -1
clrldi r25, r25, 48
and. r11, r0, r25
mfcr r12
blr
#_ REGISTER_OUT r0 0x100000FF
#_ REGISTER_OUT r25 0x0000FFFF
#_ REGISTER_OUT r11 0x000000FF
#_ REGISTER_OUT r12 0x40000000