From 5ec6b7973b53738e16c1c3700d74ea35e6b12fb9 Mon Sep 17 00:00:00 2001 From: gibbed Date: Thu, 14 May 2015 01:56:30 -0500 Subject: [PATCH] Tests for and. --- src/xenia/cpu/frontend/test/instr_and.s | 205 ++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 src/xenia/cpu/frontend/test/instr_and.s diff --git a/src/xenia/cpu/frontend/test/instr_and.s b/src/xenia/cpu/frontend/test/instr_and.s new file mode 100644 index 000000000..34555c433 --- /dev/null +++ b/src/xenia/cpu/frontend/test/instr_and.s @@ -0,0 +1,205 @@ +test_and_1: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + +test_and_1_constant: + li r5, -1 + li r25, -1 + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + +test_and_2: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r25 0 + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0 + #_ REGISTER_OUT r11 0 + +test_and_2_constant: + li r5, -1 + li r25, 0 + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0 + #_ REGISTER_OUT r11 0 + +test_and_3: + #_ REGISTER_IN r5 0 + #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + +test_and_3_constant: + li r5, 0 + li r25, -1 + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + +test_and_4: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r25 0x0000FFFF + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x0000FFFF + +test_and_4_constant: + li r5, -1 + li r25, -1 + clrldi r25, r25, 48 + and r11, r5, r25 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x0000FFFF + +test_and_5: + #_ REGISTER_IN r0 0x100000FF + #_ REGISTER_IN r25 0x0000FFFF + and r11, r0, r25 + blr + #_ REGISTER_OUT r0 0x100000FF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x000000FF + +test_and_5_constant: + lis r0, 0x1000 + ori r0, r0, 0xFF + li r25, -1 + clrldi r25, r25, 48 + and r11, r0, r25 + blr + #_ REGISTER_OUT r0 0x100000FF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x000000FF + +test_and_cr_1: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r12 0x80000000 + +test_and_cr_1_constant: + li r5, -1 + li r25, -1 + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r12 0x80000000 + +test_and_cr_2: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r25 0 + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 + +test_and_cr_2_constant: + li r5, -1 + li r25, 0 + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0 + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 + +test_and_cr_3: + #_ REGISTER_IN r5 0 + #_ REGISTER_IN r25 0xFFFFFFFFFFFFFFFF + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 + +test_and_cr_3_constant: + li r5, 0 + li r25, -1 + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r25 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r11 0 + #_ REGISTER_OUT r12 0x20000000 + +test_and_cr_4: + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r25 0x0000FFFF + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x0000FFFF + #_ REGISTER_OUT r12 0x40000000 + +test_and_cr_4_constant: + li r5, -1 + li r25, -1 + clrldi r25, r25, 48 + and. r11, r5, r25 + mfcr r12 + blr + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x0000FFFF + #_ REGISTER_OUT r12 0x40000000 + +test_and_cr_5: + #_ REGISTER_IN r0 0x100000FF + #_ REGISTER_IN r25 0x0000FFFF + and. r11, r0, r25 + mfcr r12 + blr + #_ REGISTER_OUT r0 0x100000FF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x000000FF + #_ REGISTER_OUT r12 0x40000000 + +test_and_cr_5_constant: + lis r0, 0x1000 + ori r0, r0, 0xFF + li r25, -1 + clrldi r25, r25, 48 + and. r11, r0, r25 + mfcr r12 + blr + #_ REGISTER_OUT r0 0x100000FF + #_ REGISTER_OUT r25 0x0000FFFF + #_ REGISTER_OUT r11 0x000000FF + #_ REGISTER_OUT r12 0x40000000