Discovered new GPU opcode for constant setting.
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@ -839,6 +839,9 @@ bool CommandProcessor::ExecutePacketType3(RingbufferReader* reader,
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case PM4_LOAD_ALU_CONSTANT:
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case PM4_LOAD_ALU_CONSTANT:
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result = ExecutePacketType3_LOAD_ALU_CONSTANT(reader, packet, count);
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result = ExecutePacketType3_LOAD_ALU_CONSTANT(reader, packet, count);
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break;
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break;
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case PM4_SET_SHADER_CONSTANTS:
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result = ExecutePacketType3_SET_SHADER_CONSTANTS(reader, packet, count);
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break;
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case PM4_IM_LOAD:
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case PM4_IM_LOAD:
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result = ExecutePacketType3_IM_LOAD(reader, packet, count);
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result = ExecutePacketType3_IM_LOAD(reader, packet, count);
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break;
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break;
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@ -1360,8 +1363,18 @@ bool CommandProcessor::ExecutePacketType3_LOAD_ALU_CONSTANT(
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return true;
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return true;
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}
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}
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bool CommandProcessor::ExecutePacketType3_IM_LOAD(RingbufferReader* reader,
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bool CommandProcessor::ExecutePacketType3_SET_SHADER_CONSTANTS(
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RingbufferReader* reader, uint32_t packet, uint32_t count) {
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uint32_t offset_type = reader->Read();
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uint32_t index = offset_type & 0xFFFF;
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for (uint32_t n = 0; n < count - 1; n++, index++) {
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uint32_t data = reader->Read();
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WriteRegister(index, data);
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}
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return true;
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}
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bool CommandProcessor::ExecutePacketType3_IM_LOAD(RingbufferReader* reader,
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uint32_t packet,
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uint32_t packet,
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uint32_t count) {
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uint32_t count) {
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// load sequencer instruction memory (pointer-based)
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// load sequencer instruction memory (pointer-based)
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@ -1536,8 +1549,12 @@ CommandProcessor::UpdateStatus CommandProcessor::UpdateShaders(
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// These are the constant base addresses/ranges for shaders.
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// These are the constant base addresses/ranges for shaders.
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// We have these hardcoded right now cause nothing seems to differ.
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// We have these hardcoded right now cause nothing seems to differ.
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assert_true(register_file_->values[XE_GPU_REG_SQ_VS_CONST].u32 == 0x000FF000);
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assert_true(register_file_->values[XE_GPU_REG_SQ_VS_CONST].u32 ==
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assert_true(register_file_->values[XE_GPU_REG_SQ_PS_CONST].u32 == 0x000FF100);
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0x000FF000 ||
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register_file_->values[XE_GPU_REG_SQ_VS_CONST].u32 == 0x00000000);
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assert_true(register_file_->values[XE_GPU_REG_SQ_PS_CONST].u32 ==
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0x000FF100 ||
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register_file_->values[XE_GPU_REG_SQ_PS_CONST].u32 == 0x00000000);
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bool dirty = false;
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bool dirty = false;
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dirty |=
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dirty |=
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@ -172,7 +172,8 @@ class CommandProcessor {
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bool ExecutePacketType3_SET_CONSTANT(RingbufferReader* reader,
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bool ExecutePacketType3_SET_CONSTANT(RingbufferReader* reader,
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uint32_t packet, uint32_t count);
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uint32_t packet, uint32_t count);
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bool ExecutePacketType3_LOAD_ALU_CONSTANT(RingbufferReader* reader,
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bool ExecutePacketType3_LOAD_ALU_CONSTANT(RingbufferReader* reader,
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uint32_t packet, uint32_t count);
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bool ExecutePacketType3_SET_SHADER_CONSTANTS(RingbufferReader* reader,
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uint32_t packet, uint32_t count);
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uint32_t packet, uint32_t count);
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bool ExecutePacketType3_IM_LOAD(RingbufferReader* reader, uint32_t packet,
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bool ExecutePacketType3_IM_LOAD(RingbufferReader* reader, uint32_t packet,
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uint32_t count);
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uint32_t count);
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@ -405,6 +405,7 @@ enum Type3Opcode {
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PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs
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PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs
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PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory
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PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory
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PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory
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PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory
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PM4_SET_SHADER_CONSTANTS = 0x56, // ?? constant values
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PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based)
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PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based)
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PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet)
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PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet)
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PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory
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PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory
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