From 341a493bf983f901d4c8329c7a8d8a891cef0938 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sun, 15 Mar 2015 12:26:40 -0700 Subject: [PATCH] Discovered new GPU opcode for constant setting. --- src/xenia/gpu/gl4/command_processor.cc | 23 ++++++++++++++++++++--- src/xenia/gpu/gl4/command_processor.h | 3 ++- src/xenia/gpu/xenos.h | 1 + 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/src/xenia/gpu/gl4/command_processor.cc b/src/xenia/gpu/gl4/command_processor.cc index 3e21f7b99..16d61837f 100644 --- a/src/xenia/gpu/gl4/command_processor.cc +++ b/src/xenia/gpu/gl4/command_processor.cc @@ -839,6 +839,9 @@ bool CommandProcessor::ExecutePacketType3(RingbufferReader* reader, case PM4_LOAD_ALU_CONSTANT: result = ExecutePacketType3_LOAD_ALU_CONSTANT(reader, packet, count); break; + case PM4_SET_SHADER_CONSTANTS: + result = ExecutePacketType3_SET_SHADER_CONSTANTS(reader, packet, count); + break; case PM4_IM_LOAD: result = ExecutePacketType3_IM_LOAD(reader, packet, count); break; @@ -1360,8 +1363,18 @@ bool CommandProcessor::ExecutePacketType3_LOAD_ALU_CONSTANT( return true; } -bool CommandProcessor::ExecutePacketType3_IM_LOAD(RingbufferReader* reader, +bool CommandProcessor::ExecutePacketType3_SET_SHADER_CONSTANTS( + RingbufferReader* reader, uint32_t packet, uint32_t count) { + uint32_t offset_type = reader->Read(); + uint32_t index = offset_type & 0xFFFF; + for (uint32_t n = 0; n < count - 1; n++, index++) { + uint32_t data = reader->Read(); + WriteRegister(index, data); + } + return true; +} +bool CommandProcessor::ExecutePacketType3_IM_LOAD(RingbufferReader* reader, uint32_t packet, uint32_t count) { // load sequencer instruction memory (pointer-based) @@ -1536,8 +1549,12 @@ CommandProcessor::UpdateStatus CommandProcessor::UpdateShaders( // These are the constant base addresses/ranges for shaders. // We have these hardcoded right now cause nothing seems to differ. - assert_true(register_file_->values[XE_GPU_REG_SQ_VS_CONST].u32 == 0x000FF000); - assert_true(register_file_->values[XE_GPU_REG_SQ_PS_CONST].u32 == 0x000FF100); + assert_true(register_file_->values[XE_GPU_REG_SQ_VS_CONST].u32 == + 0x000FF000 || + register_file_->values[XE_GPU_REG_SQ_VS_CONST].u32 == 0x00000000); + assert_true(register_file_->values[XE_GPU_REG_SQ_PS_CONST].u32 == + 0x000FF100 || + register_file_->values[XE_GPU_REG_SQ_PS_CONST].u32 == 0x00000000); bool dirty = false; dirty |= diff --git a/src/xenia/gpu/gl4/command_processor.h b/src/xenia/gpu/gl4/command_processor.h index cdc57ff1c..dfabbf3fe 100644 --- a/src/xenia/gpu/gl4/command_processor.h +++ b/src/xenia/gpu/gl4/command_processor.h @@ -172,8 +172,9 @@ class CommandProcessor { bool ExecutePacketType3_SET_CONSTANT(RingbufferReader* reader, uint32_t packet, uint32_t count); bool ExecutePacketType3_LOAD_ALU_CONSTANT(RingbufferReader* reader, - uint32_t packet, uint32_t count); + bool ExecutePacketType3_SET_SHADER_CONSTANTS(RingbufferReader* reader, + uint32_t packet, uint32_t count); bool ExecutePacketType3_IM_LOAD(RingbufferReader* reader, uint32_t packet, uint32_t count); bool ExecutePacketType3_IM_LOAD_IMMEDIATE(RingbufferReader* reader, diff --git a/src/xenia/gpu/xenos.h b/src/xenia/gpu/xenos.h index 0c516a619..c9dcbeead 100644 --- a/src/xenia/gpu/xenos.h +++ b/src/xenia/gpu/xenos.h @@ -405,6 +405,7 @@ enum Type3Opcode { PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory + PM4_SET_SHADER_CONSTANTS = 0x56, // ?? constant values PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based) PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet) PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory