vspltis[bhw] tests.

src/alloy/frontend/ppc/test/bin/instr_vspltisb.dis

@@ -0,0 +1,21 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltisb.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vspltisb_1>:
+  100000:	10 60 03 0c 	vspltisb v3,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vspltisb_2>:
+  100008:	10 61 03 0c 	vspltisb v3,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vspltisb_3>:
+  100010:	10 7f 03 0c 	vspltisb v3,-1
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vspltisb_4>:
+  100018:	10 7e 03 0c 	vspltisb v3,-2
+  10001c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vspltisb.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_vspltisb_1
+0000000000000008 t test_vspltisb_2
+0000000000000010 t test_vspltisb_3
+0000000000000018 t test_vspltisb_4

src/alloy/frontend/ppc/test/bin/instr_vspltish.dis

@@ -0,0 +1,21 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltish.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vspltish_1>:
+  100000:	10 60 03 4c 	vspltish v3,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vspltish_2>:
+  100008:	10 61 03 4c 	vspltish v3,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vspltish_3>:
+  100010:	10 7f 03 4c 	vspltish v3,-1
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vspltish_4>:
+  100018:	10 7e 03 4c 	vspltish v3,-2
+  10001c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vspltish.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_vspltish_1
+0000000000000008 t test_vspltish_2
+0000000000000010 t test_vspltish_3
+0000000000000018 t test_vspltish_4

src/alloy/frontend/ppc/test/bin/instr_vspltisw.dis

@@ -0,0 +1,21 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vspltisw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vspltisw_1>:
+  100000:	10 60 03 8c 	vspltisw v3,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vspltisw_2>:
+  100008:	10 61 03 8c 	vspltisw v3,1
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vspltisw_3>:
+  100010:	10 7f 03 8c 	vspltisw v3,-1
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vspltisw_4>:
+  100018:	10 7e 03 8c 	vspltisw v3,-2
+  10001c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_vspltisw.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_vspltisw_1
+0000000000000008 t test_vspltisw_2
+0000000000000010 t test_vspltisw_3
+0000000000000018 t test_vspltisw_4

src/alloy/frontend/ppc/test/instr_vspltisb.s

@@ -0,0 +1,19 @@
+test_vspltisb_1:
+  vspltisb v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+
+test_vspltisb_2:
+  vspltisb v3, 1
+  blr
+  #_ REGISTER_OUT v3 [01010101, 01010101, 01010101, 01010101]
+
+test_vspltisb_3:
+  vspltisb v3, -1
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vspltisb_4:
+  vspltisb v3, -2
+  blr
+  #_ REGISTER_OUT v3 [FEFEFEFE, FEFEFEFE, FEFEFEFE, FEFEFEFE]

src/alloy/frontend/ppc/test/instr_vspltish.s

@@ -0,0 +1,19 @@
+test_vspltish_1:
+  vspltish v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+
+test_vspltish_2:
+  vspltish v3, 1
+  blr
+  #_ REGISTER_OUT v3 [00010001, 00010001, 00010001, 00010001]
+
+test_vspltish_3:
+  vspltish v3, -1
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vspltish_4:
+  vspltish v3, -2
+  blr
+  #_ REGISTER_OUT v3 [FFFEFFFE, FFFEFFFE, FFFEFFFE, FFFEFFFE]

src/alloy/frontend/ppc/test/instr_vspltisw.s

@@ -0,0 +1,19 @@
+test_vspltisw_1:
+  vspltisw v3, 0
+  blr
+  #_ REGISTER_OUT v3 [00000000, 00000000, 00000000, 00000000]
+
+test_vspltisw_2:
+  vspltisw v3, 1
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000001, 00000001, 00000001]
+
+test_vspltisw_3:
+  vspltisw v3, -1
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
+
+test_vspltisw_4:
+  vspltisw v3, -2
+  blr
+  #_ REGISTER_OUT v3 [FFFFFFFE, FFFFFFFE, FFFFFFFE, FFFFFFFE]