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[a64] Fix `SELECT_V128_V128` 

Potential input-register stomping and operand order is seemingly wrong.

Passes generated unit tests.
This commit is contained in:
Wunkolo 2024-05-10 21:57:05 -07:00
parent de040f0b42
commit 1ad0d7e514
1 changed files with 4 additions and 2 deletions
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6
src/xenia/cpu/backend/a64/a64_sequences.cc
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@ -720,9 +720,11 @@ struct SELECT_V128_V128
: Sequence<SELECT_V128_V128, : Sequence<SELECT_V128_V128,
I<OPCODE_SELECT, V128Op, V128Op, V128Op, V128Op>> { I<OPCODE_SELECT, V128Op, V128Op, V128Op, V128Op>> {
static void Emit(A64Emitter& e, const EmitArgType& i) { static void Emit(A64Emitter& e, const EmitArgType& i) {
const QReg src1 = i.src1.is_constant ? Q0 : i.src1; const QReg src1 = Q0;
if (i.src1.is_constant) { if (i.src1.is_constant) {
e.LoadConstantV(src1, i.src1.constant()); e.LoadConstantV(src1, i.src1.constant());
} else {
e.MOV(src1.B16(), i.src1.reg().B16());
} }
const QReg src2 = i.src2.is_constant ? Q1 : i.src2; const QReg src2 = i.src2.is_constant ? Q1 : i.src2;
@ -736,7 +738,7 @@ struct SELECT_V128_V128
} }
// src1 ? src2 : src3; // src1 ? src2 : src3;
e.BSL(src1.B16(), src2.B16(), src3.B16()); e.BSL(src1.B16(), src3.B16(), src2.B16());
e.MOV(i.dest.reg().B16(), src1.B16()); e.MOV(i.dest.reg().B16(), src1.B16());
} }
}; };