From 1ad0d7e514d050dff149caa1834730089f96b120 Mon Sep 17 00:00:00 2001
From: Wunkolo <Wunkolo@gmail.com>
Date: Fri, 10 May 2024 21:57:05 -0700
Subject: [PATCH] [a64] Fix `SELECT_V128_V128`

Potential input-register stomping and operand order is seemingly wrong.

Passes generated unit tests.
---
 src/xenia/cpu/backend/a64/a64_sequences.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/xenia/cpu/backend/a64/a64_sequences.cc b/src/xenia/cpu/backend/a64/a64_sequences.cc
index 2a2f64a35..df11306d1 100644
--- a/src/xenia/cpu/backend/a64/a64_sequences.cc
+++ b/src/xenia/cpu/backend/a64/a64_sequences.cc
@@ -720,9 +720,11 @@ struct SELECT_V128_V128
     : Sequence<SELECT_V128_V128,
                I<OPCODE_SELECT, V128Op, V128Op, V128Op, V128Op>> {
   static void Emit(A64Emitter& e, const EmitArgType& i) {
-    const QReg src1 = i.src1.is_constant ? Q0 : i.src1;
+    const QReg src1 = Q0;
     if (i.src1.is_constant) {
       e.LoadConstantV(src1, i.src1.constant());
+    } else {
+      e.MOV(src1.B16(), i.src1.reg().B16());
     }
 
     const QReg src2 = i.src2.is_constant ? Q1 : i.src2;
@@ -736,7 +738,7 @@ struct SELECT_V128_V128
     }
 
     // src1 ? src2 : src3;
-    e.BSL(src1.B16(), src2.B16(), src3.B16());
+    e.BSL(src1.B16(), src3.B16(), src2.B16());
     e.MOV(i.dest.reg().B16(), src1.B16());
   }
 };