PM4_LOAD_ALU_CONSTANT
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7d6dda356c
commit
0355047838
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@ -569,13 +569,13 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
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uint32_t type = (offset_type >> 16) & 0xFF;
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switch (type) {
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case 0x4: // REGISTER
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index += 0x2000;
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index += 0x2000; // registers
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for (uint32_t n = 0; n < count - 1; n++, index++) {
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uint32_t data = READ_PTR();
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const char* reg_name = xenos::GetRegisterName(index);
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XELOGGPU("[%.8X] %.8X -> %.4X %s",
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packet_ptr + (1 + n) * 4,
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data, index, reg_name? reg_name : "");
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data, index, reg_name ? reg_name : "");
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WriteRegister(packet_ptr, index, data);
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}
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break;
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@ -585,6 +585,29 @@ uint32_t RingBufferWorker::ExecutePacket(PacketArgs& args) {
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}
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}
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break;
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case PM4_LOAD_ALU_CONSTANT:
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// load constants from memory
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{
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XELOGGPU("[%.8X] Packet(%.8X): PM4_LOAD_ALU_CONSTANT",
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packet_ptr, packet);
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uint32_t address = READ_PTR();
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address &= 0x3FFFFFFF;
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uint32_t offset_type = READ_PTR();
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uint32_t index = offset_type & 0x7FF;
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uint32_t size = READ_PTR();
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size &= 0xFFF;
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index += 0x4000; // alu constants
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for (uint32_t n = 0; n < size; n++, index++) {
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uint32_t data = XEGETUINT32BE(
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p + GpuToCpu(packet_ptr, address + n * 4));
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const char* reg_name = xenos::GetRegisterName(index);
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XELOGGPU("[%.8X] %.8X -> %.4X %s",
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packet_ptr,
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data, index, reg_name ? reg_name : "");
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WriteRegister(packet_ptr, index, data);
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}
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}
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break;
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case PM4_IM_LOAD:
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// load sequencer instruction memory (pointer-based)
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@ -56,6 +56,7 @@ enum Type3Opcode {
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PM4_VIZ_QUERY = 0x23, // begin/end initiator for viz query extent processing
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PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs
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PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory
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PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory
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PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based)
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PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet)
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PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory
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