140 lines
6.0 KiB
Markdown
140 lines
6.0 KiB
Markdown
# CPU Documentation
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## The JIT
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The JIT is the core of Xenia. It translates Xenon PowerPC code into native
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code runnable on the host computer.
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There are 3 phases to translation:
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1. Translation to IR (intermediate representation)
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2. IR compilation/optimization
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3. Backend emission
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PowerPC instructions are translated to Xenia's intermediate representation
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format in src/xenia/cpu/ppc/ppc_emit_*.cc (e.g. processor control is done in
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[ppc_emit_control.cc](../src/xenia/cpu/ppc/ppc_emit_control.cc)). HIR opcodes
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are relatively simple opcodes such that any host can define an implementation.
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After the HIR is generated, it is ran through a compiler to prep it for generation.
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The compiler is ran in a series of passes, the order of which is defined in
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[ppc_translator.cc](../src/xenia/cpu/ppc/ppc_translator.cc). Some passes are
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essential to the successful generation, while others are merely for optimization
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purposes. Compiler passes are defined in src/xenia/cpu/compiler/passes with
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descriptive class names.
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Finally, the backend consumes the HIR and emits code that runs natively on the
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host. Currently, the only backend that exists is the x64 backend, with all the
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emission done in
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[x64_sequences.cc](../src/xenia/cpu/backend/x64/x64_sequences.cc).
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## ABI
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Xenia guest functions are not directly callable, but rather must be called
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through APIs provided by Xenia. Xenia will first execute a thunk to transition
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the host context to a state dependent on the JIT backend, and that will call the
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guest code.
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### x64
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Transition thunks defined in [x64_backend.cc](../src/xenia/cpu/backend/x64/x64_backend.cc#L389).
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Registers are stored on the stack as defined by [StackLayout::Thunk](../src/xenia/cpu/backend/x64/x64_stack_layout.h#L96)
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for later transitioning back to the host.
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Some registers are reserved for usage by the JIT to store temporary variables.
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See: [X64Emitter::gpr_reg_map_ and X64Emitter::xmm_reg_map_](../src/xenia/cpu/backend/x64/x64_emitter.cc#L57).
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#### Integer Registers
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Register | Usage
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--- | ---
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RAX | Scratch
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RBX | JIT temp
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RCX | Scratch
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RDX | Scratch
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RSP | Stack Pointer
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RBP | Unused
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RSI | PowerPC Context
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RDI | Virtual Memory Base
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R8-R11 | Unused (parameters)
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R12-R15 | JIT temp
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#### Floating Point Registers
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Register | Usage
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--- | ---
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XMM0-XMM5 | Scratch
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XMM6-XMM15 | JIT temp
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## Memory
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Xenia defines virtual memory as a mapped range beginning at Memory::virtual_membase(),
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and physical memory as another mapped range from Memory::physical_membase()
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(usually 0x100000000 and 0x200000000, respectively). If the default bases are
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not available, they are shifted left 1 bit until an available range is found.
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The guest only has access to these ranges, nothing else.
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### Map
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```
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0x00000000 - 0x3FFFFFFF (1024mb) - virtual 4k pages
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0x40000000 - 0x7FFFFFFF (1024mb) - virtual 64k pages
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0x80000000 - 0x8BFFFFFF ( 192mb) - xex 64k pages
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0x8C000000 - 0x8FFFFFFF ( 64mb) - xex 64k pages (encrypted)
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0x90000000 - 0x9FFFFFFF ( 256mb) - xex 4k pages
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0xA0000000 - 0xBFFFFFFF ( 512mb) - physical 64k pages (overlapped)
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0xC0000000 - 0xDFFFFFFF - physical 16mb pages (overlapped)
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0xE0000000 - 0xFFFFFFFF - physical 4k pages (overlapped)
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```
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Virtual pages are usually allocated by NtAllocateVirtualMemory, and
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physical pages are usually allocated by MmAllocatePhysicalMemoryEx.
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Virtual pages mapped to physical memory are also mapped to the physical membase,
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i.e. virtual 0xA0000000 == physical 0x00000000
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The 0xE0000000-0xFFFFFFFF range is mapped to physical memory with a single 4 KB
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page offset. On Windows, memory mappings must be aligned to 64 KB, so the offset
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has to be added when guest addresses are converted to host addresses in the
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translated CPU code. This can't be faked other ways because calculations
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involving the offset are built into games - see the following sequence:
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```
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srwi r9, r10, 20 # r9 = r10 >> 20
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clrlwi r10, r10, 3 # r10 = r10 & 0x1FFFFFFF (physical address)
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addi r11, r9, 0x200
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rlwinm r11, r11, 0,19,19 # r11 = r11 & 0x1000
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add r11, r11, r10 # add 1 page to addresses > 0xE0000000
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# r11 = addess passed to GPU
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```
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## Memory Management
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TODO
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## References
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### PowerPC
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The processor in the 360 is a 64-bit PowerPC chip running in 32-bit mode.
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Programs are still allowed to use 64-bit PowerPC instructions, and registers
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are 64-bit as well, but 32-bit instructions will run in 32-bit mode.
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The CPU is largely similar to the PPC part in the PS3, so Cell documents
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often line up for the core instructions. The 360 adds some additional AltiVec
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instructions, though, which are only documented in a few places (like the gcc source code, etc).
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* [Free60 Info](https://free60project.github.io/wiki/Xenon_(CPU))
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* [Power ISA docs](https://web.archive.org/web/20140603115759/https://www.power.org/wp-content/uploads/2012/07/PowerISA_V2.06B_V2_PUBLIC.pdf) (aka 'PowerISA')
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* [PowerPC Programming Environments Manual](https://web.archive.org/web/20141028181028/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/F7E732FF811F783187256FDD004D3797/$file/pem_64bit_v3.0.2005jul15.pdf) (aka 'pem_64')
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* [PowerPC Vector PEM](https://web.archive.org/web/20130502201029/https://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/C40E4C6133B31EE8872570B500791108/$file/vector_simd_pem_v_2.07c_26Oct2006_cell.pdf)
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* [AltiVec PEM](https://web.archive.org/web/20151110180336/https://cache.freescale.com/files/32bit/doc/ref_manual/ALTIVECPEM.pdf)
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* [VMX128 Opcodes](http://biallas.net/doc/vmx128/vmx128.txt)
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* [AltiVec Decoding](https://github.com/kakaroto/ps3ida/blob/master/plugins/PPCAltivec/src/main.cpp)
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### x64
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* [Intel Manuals](https://software.intel.com/en-us/articles/intel-sdm)
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* [Combined Intel Manuals](https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf)
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* [Apple AltiVec/SSE Migration Guide](https://developer.apple.com/legacy/library/documentation/Performance/Conceptual/Accelerate_sse_migration/Accelerate_sse_migration.pdf)
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