Adding basic register names.
This commit is contained in:
Ben Vanik
parent
e00e665a09
commit
cf57481a0e
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@ -127,7 +127,9 @@ void RingBufferWorker::ExecuteSegment(uint32_t ptr, uint32_t length) {
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uint32_t base_index = (packet & 0xFFFF);
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for (uint32_t m = 0; m < count; m++) {
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uint32_t reg_data = XEGETUINT32BE(packet_base + 1 * 4 + m * 4);
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XELOGGPU(" %.4X <- %.8X", base_index + m, reg_data);
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const char* reg_name = xenos::GetRegisterName(base_index + m);
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XELOGGPU(" %.8X -> %.4X %s", reg_data, base_index + m,
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reg_name ? reg_name : "");
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// TODO(benvanik): process register writes.
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}
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n += 1 + count;
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@ -142,8 +144,12 @@ void RingBufferWorker::ExecuteSegment(uint32_t ptr, uint32_t length) {
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uint32_t reg_index_2 = (packet >> 11) & 0x7FF;
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uint32_t reg_data_1 = XEGETUINT32BE(packet_base + 1 * 4);
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uint32_t reg_data_2 = XEGETUINT32BE(packet_base + 2 * 4);
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XELOGGPU(" %.4X <- %.8X", reg_index_1, reg_data_1);
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XELOGGPU(" %.4X <- %.8X", reg_index_2, reg_data_2);
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const char* reg_name_1 = xenos::GetRegisterName(reg_index_1);
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const char* reg_name_2 = xenos::GetRegisterName(reg_index_2);
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XELOGGPU(" %.8X -> %.4X %s", reg_data_1, reg_index_1,
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reg_name_1 ? reg_name_1 : "");
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XELOGGPU(" %.8X -> %.4X %s", reg_data_2, reg_index_2,
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reg_name_2 ? reg_name_2 : "");
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// TODO(benvanik): process register writes.
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n += 1 + 2;
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}
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@ -0,0 +1,176 @@
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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// This is a partial file designed to be included by other files when
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// constructing various tables.
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// Almost all of these values are taken directly from:
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// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h
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//#define XE_GPU_REGISTER(index, type, name)
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XE_GPU_REGISTER(0x01DD, dword, SCRATCH_ADDR)
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XE_GPU_REGISTER(0x01DC, dword, SCRATCH_UMSK)
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XE_GPU_REGISTER(0x0578, dword, SCRATCH_REG0)
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XE_GPU_REGISTER(0x0579, dword, SCRATCH_REG1)
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XE_GPU_REGISTER(0x057A, dword, SCRATCH_REG2)
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XE_GPU_REGISTER(0x057B, dword, SCRATCH_REG3)
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XE_GPU_REGISTER(0x057C, dword, SCRATCH_REG4)
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XE_GPU_REGISTER(0x057D, dword, SCRATCH_REG5)
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XE_GPU_REGISTER(0x057E, dword, SCRATCH_REG6)
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XE_GPU_REGISTER(0x057F, dword, SCRATCH_REG7)
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XE_GPU_REGISTER(0x05C8, dword, WAIT_UNTIL)
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XE_GPU_REGISTER(0x0A02, dword, UNKNOWN_0A02)
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XE_GPU_REGISTER(0x0A03, dword, UNKNOWN_0A03)
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XE_GPU_REGISTER(0x0A04, dword, UNKNOWN_0A04)
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XE_GPU_REGISTER(0x0A05, dword, UNKNOWN_0A05)
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XE_GPU_REGISTER(0x0A2F, dword, COHER_SIZE_HOST)
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XE_GPU_REGISTER(0x0A30, dword, COHER_BASE_HOST)
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XE_GPU_REGISTER(0x0A31, dword, COHER_STATUS_HOST)
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XE_GPU_REGISTER(0x0D01, dword, SQ_FLOW_CONTROL)
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XE_GPU_REGISTER(0x0D02, dword, SQ_INST_STORE_MANAGMENT)
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XE_GPU_REGISTER(0x0D04, dword, SQ_EO_RT)
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XE_GPU_REGISTER(0x0C85, dword, PA_CL_ENHANCE)
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XE_GPU_REGISTER(0x0E42, dword, UNKNOWN_0E42)
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XE_GPU_REGISTER(0x0F01, dword, RB_BC_CONTROL)
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XE_GPU_REGISTER(0x200D, dword, COHER_DEST_BASE_7)
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XE_GPU_REGISTER(0x2080, dword, PA_SC_WINDOW_OFFSET)
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XE_GPU_REGISTER(0x2081, dword, PA_SC_WINDOW_SCISSOR_TL)
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XE_GPU_REGISTER(0x2082, dword, PA_SC_WINDOW_SCISSOR_BR)
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XE_GPU_REGISTER(0x2100, dword, VGT_MAX_VTX_INDX)
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XE_GPU_REGISTER(0x2101, dword, VGT_MIN_VTX_INDX)
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XE_GPU_REGISTER(0x2102, dword, VGT_INDX_OFFSET)
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XE_GPU_REGISTER(0x2103, dword, VGT_MULTI_PRIM_IB_RESET_INDX)
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XE_GPU_REGISTER(0x2104, dword, RB_COLOR_MASK)
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XE_GPU_REGISTER(0x2105, float, RB_BLEND_RED)
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XE_GPU_REGISTER(0x2106, float, RB_BLEND_GREEN)
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XE_GPU_REGISTER(0x2107, float, RB_BLEND_BLUE)
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XE_GPU_REGISTER(0x2108, float, RB_BLEND_ALPHA)
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XE_GPU_REGISTER(0x2109, float, RB_FOG_COLOR_RED)
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XE_GPU_REGISTER(0x210A, float, RB_FOG_COLOR_GREEN)
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XE_GPU_REGISTER(0x210B, float, RB_FOG_COLOR_BLUE)
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XE_GPU_REGISTER(0x210C, dword, RB_STENCILREFMASK_BF)
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XE_GPU_REGISTER(0x210D, dword, RB_STENCILREFMASK)
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XE_GPU_REGISTER(0x210E, float, RB_ALPHA_REF)
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XE_GPU_REGISTER(0x210F, float, PA_CL_VPORT_XSCALE)
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XE_GPU_REGISTER(0x2110, float, PA_CL_VPORT_XOFFSET)
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XE_GPU_REGISTER(0x2111, float, PA_CL_VPORT_YSCALE)
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XE_GPU_REGISTER(0x2112, float, PA_CL_VPORT_YOFFSET)
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XE_GPU_REGISTER(0x2113, float, PA_CL_VPORT_ZSCALE)
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XE_GPU_REGISTER(0x2114, float, PA_CL_VPORT_ZOFFSET)
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XE_GPU_REGISTER(0x2180, dword, SQ_PROGRAM_CNTL)
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XE_GPU_REGISTER(0x2181, dword, SQ_CONTEXT_MISC)
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XE_GPU_REGISTER(0x2182, dword, SQ_INTERPOLATOR_CNTL)
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XE_GPU_REGISTER(0x2183, dword, SQ_WRAPPING_0)
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XE_GPU_REGISTER(0x2184, dword, SQ_WRAPPING_1)
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XE_GPU_REGISTER(0x2200, dword, RB_DEPTHCONTROL)
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XE_GPU_REGISTER(0x2201, dword, RB_BLENDCONTROL_0)
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XE_GPU_REGISTER(0x2202, dword, RB_COLORCONTROL)
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XE_GPU_REGISTER(0x2203, dword, VGT_CURRENT_BIN_ID_MAX)
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XE_GPU_REGISTER(0x2204, dword, PA_CL_CLIP_CNTL)
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XE_GPU_REGISTER(0x2205, dword, PA_SU_SC_MODE_CNTL)
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XE_GPU_REGISTER(0x2206, dword, PA_CL_VTE_CNTL)
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XE_GPU_REGISTER(0x2207, dword, VGT_CURRENT_BIN_ID_MIN)
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XE_GPU_REGISTER(0x2208, dword, RB_MODECONTROL)
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XE_GPU_REGISTER(0x2209, dword, RB_BLENDCONTROL_1)
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XE_GPU_REGISTER(0x220A, dword, RB_BLENDCONTROL_2)
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XE_GPU_REGISTER(0x220B, dword, RB_BLENDCONTROL_3)
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XE_GPU_REGISTER(0x2280, dword, PA_SU_POINT_SIZE)
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XE_GPU_REGISTER(0x2281, dword, PA_SU_POINT_MINMAX)
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XE_GPU_REGISTER(0x2282, dword, PA_SU_LINE_CNTL)
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XE_GPU_REGISTER(0x2283, dword, PA_SC_LINE_STIPPLE)
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XE_GPU_REGISTER(0x2284, dword, UNKNOWN_2284)
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XE_GPU_REGISTER(0x2285, dword, UNKNOWN_2285)
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XE_GPU_REGISTER(0x2286, float, UNKNOWN_2286)
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XE_GPU_REGISTER(0x2287, float, UNKNOWN_2287)
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XE_GPU_REGISTER(0x2288, dword, UNKNOWN_2288)
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XE_GPU_REGISTER(0x2289, dword, UNKNOWN_2289)
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XE_GPU_REGISTER(0x228A, dword, UNKNOWN_228A)
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XE_GPU_REGISTER(0x228B, dword, UNKNOWN_228B)
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XE_GPU_REGISTER(0x228C, dword, UNKNOWN_228C)
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XE_GPU_REGISTER(0x228D, dword, UNKNOWN_228D)
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XE_GPU_REGISTER(0x228E, dword, UNKNOWN_228E)
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XE_GPU_REGISTER(0x228F, dword, UNKNOWN_228F)
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XE_GPU_REGISTER(0x2290, dword, UNKNOWN_2290)
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XE_GPU_REGISTER(0x2291, dword, UNKNOWN_2291)
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XE_GPU_REGISTER(0x2292, dword, UNKNOWN_2292)
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XE_GPU_REGISTER(0x2293, dword, PA_SC_VIZ_QUERY)
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XE_GPU_REGISTER(0x2294, dword, VGT_ENHANCE)
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XE_GPU_REGISTER(0x2300, dword, PA_SC_LINE_CNTL)
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XE_GPU_REGISTER(0x2301, dword, PA_SC_AA_CONFIG)
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XE_GPU_REGISTER(0x2302, dword, PA_SU_VTX_CNTL)
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XE_GPU_REGISTER(0x2303, float, PA_CL_GB_VERT_CLIP_ADJ)
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XE_GPU_REGISTER(0x2304, float, PA_CL_GB_VERT_DISC_ADJ)
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XE_GPU_REGISTER(0x2305, float, PA_CL_GB_HORZ_CLIP_ADJ)
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XE_GPU_REGISTER(0x2306, float, PA_CL_GB_HORZ_DISC_ADJ)
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XE_GPU_REGISTER(0x2307, dword, SQ_VS_CONST)
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XE_GPU_REGISTER(0x2308, dword, SQ_PS_CONST)
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XE_GPU_REGISTER(0x2309, dword, SQ_DEBUG_MISC_0)
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XE_GPU_REGISTER(0x230A, dword, SQ_DEBUG_MISC_1)
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XE_GPU_REGISTER(0x230B, dword, UNKNOWN_230B)
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XE_GPU_REGISTER(0x230C, dword, UNKNOWN_230C)
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XE_GPU_REGISTER(0x230D, dword, UNKNOWN_230D)
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XE_GPU_REGISTER(0x230E, dword, UNKNOWN_230E)
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XE_GPU_REGISTER(0x230F, dword, UNKNOWN_230F)
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XE_GPU_REGISTER(0x2310, dword, UNKNOWN_2310)
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XE_GPU_REGISTER(0x2311, dword, UNKNOWN_2311)
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XE_GPU_REGISTER(0x2312, dword, PA_SC_AA_MASK)
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XE_GPU_REGISTER(0x2313, dword, UNKNOWN_2313)
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XE_GPU_REGISTER(0x2314, dword, UNKNOWN_2314)
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XE_GPU_REGISTER(0x2315, dword, SQ_CF_PROGRAM_SIZE)
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XE_GPU_REGISTER(0x2316, dword, VGT_VERTEX_REUSE_BLOCK_CNTL)
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XE_GPU_REGISTER(0x2317, dword, VGT_OUT_DEALLOC_CNTL)
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XE_GPU_REGISTER(0x2318, dword, RB_COPY_CONTROL)
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XE_GPU_REGISTER(0x2319, dword, RB_COPY_DEST_BASE)
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XE_GPU_REGISTER(0x231A, dword, RB_COPY_DEST_PITCH)
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XE_GPU_REGISTER(0x231B, dword, RB_COPY_DEST_INFO)
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XE_GPU_REGISTER(0x231C, dword, RB_HI_CLEAR)
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XE_GPU_REGISTER(0x231D, dword, RB_DEPTH_CLEAR)
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XE_GPU_REGISTER(0x231E, dword, RB_COLOR_CLEAR)
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XE_GPU_REGISTER(0x231F, dword, RB_COLOR_CLEAR_LOW)
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XE_GPU_REGISTER(0x2320, dword, UNKNOWN_2320)
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XE_GPU_REGISTER(0x2321, dword, UNKNOWN_2321)
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XE_GPU_REGISTER(0x2322, dword, UNKNOWN_2322)
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XE_GPU_REGISTER(0x2323, dword, UNKNOWN_2323)
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XE_GPU_REGISTER(0x2324, dword, RB_SAMPLE_COUNT_CTL)
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XE_GPU_REGISTER(0x2325, dword, RB_SAMPLE_COUNT_ADDR)
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XE_GPU_REGISTER(0x2380, float, PA_SU_POLY_OFFSET_FRONT_SCALE)
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XE_GPU_REGISTER(0x2381, float, PA_SU_POLY_OFFSET_FRONT_OFFSET)
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XE_GPU_REGISTER(0x2382, float, PA_SU_POLY_OFFSET_BACK_SCALE)
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XE_GPU_REGISTER(0x2383, float, PA_SU_POLY_OFFSET_BACK_OFFSET)
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XE_GPU_REGISTER(0x2384, float, UNKNOWN_2384)
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XE_GPU_REGISTER(0x2385, float, UNKNOWN_2385)
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XE_GPU_REGISTER(0x2386, float, UNKNOWN_2386)
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XE_GPU_REGISTER(0x2387, float, UNKNOWN_2387)
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// Ignored because I have no clue what these are.
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// XE_GPU_REGISTER(0x8D00, dword, UNKNOWN_8D00)
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// XE_GPU_REGISTER(0x8D01, dword, UNKNOWN_8D01)
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// XE_GPU_REGISTER(0x8D02, dword, UNKNOWN_8D02)
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// XE_GPU_REGISTER(0x8D03, dword, UNKNOWN_8D03)
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// XE_GPU_REGISTER(0x8D04, dword, UNKNOWN_8D04)
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// XE_GPU_REGISTER(0x8D05, dword, UNKNOWN_8D05)
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// XE_GPU_REGISTER(0x8D06, dword, UNKNOWN_8D06)
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// XE_GPU_REGISTER(0x8D07, dword, UNKNOWN_8D07)
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@ -0,0 +1,27 @@
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2013 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#include <xenia/gpu/xenos/registers.h>
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using namespace xe;
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using namespace xe::gpu;
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using namespace xe::gpu::xenos;
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const char* xe::gpu::xenos::GetRegisterName(uint32_t index) {
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switch (index) {
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#define XE_GPU_REGISTER(index, type, name) \
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case index: return #name;
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#include <xenia/gpu/xenos/register_table.inc>
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#undef XE_GPU_REGISTER
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default:
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return NULL;
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}
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}
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@ -18,15 +18,28 @@ namespace gpu {
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namespace xenos {
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static const uint32_t kXEGpuRegisterCount = 0x3000;
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enum Registers {
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#define XE_GPU_REGISTER(index, type, name) \
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XE_GPU_REG_##name = index,
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#include <xenia/gpu/xenos/register_table.inc>
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#undef XE_GPU_REGISTER
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};
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const char* GetRegisterName(uint32_t index);
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union RegisterValue {
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uint32_t uint_value;
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uint32_t dword_value;
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float float_value;
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};
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struct RegisterFile {
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// TODO(benvanik): figure out the actual number.
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RegisterValue registers[0xFFFF];
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RegisterValue registers[kXEGpuRegisterCount];
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};
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@ -2,6 +2,7 @@
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{
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'sources': [
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'packets.h',
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'registers.cc',
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'registers.h',
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],
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}
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Loading…
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