diff --git a/src/xenia/gpu/ring_buffer_worker.cc b/src/xenia/gpu/ring_buffer_worker.cc
index fcccaf657..58a9000eb 100644
--- a/src/xenia/gpu/ring_buffer_worker.cc
+++ b/src/xenia/gpu/ring_buffer_worker.cc
@@ -127,7 +127,9 @@ void RingBufferWorker::ExecuteSegment(uint32_t ptr, uint32_t length) {
         uint32_t base_index = (packet & 0xFFFF);
         for (uint32_t m = 0; m < count; m++) {
           uint32_t reg_data = XEGETUINT32BE(packet_base + 1 * 4 + m * 4);
-          XELOGGPU("  %.4X <- %.8X", base_index + m, reg_data);
+          const char* reg_name = xenos::GetRegisterName(base_index + m);
+          XELOGGPU("  %.8X -> %.4X %s", reg_data, base_index + m,
+                                        reg_name ? reg_name : "");
           // TODO(benvanik): process register writes.
         }
         n += 1 + count;
@@ -142,8 +144,12 @@ void RingBufferWorker::ExecuteSegment(uint32_t ptr, uint32_t length) {
         uint32_t reg_index_2 = (packet >> 11) & 0x7FF;
         uint32_t reg_data_1 = XEGETUINT32BE(packet_base + 1 * 4);
         uint32_t reg_data_2 = XEGETUINT32BE(packet_base + 2 * 4);
-        XELOGGPU("  %.4X <- %.8X", reg_index_1, reg_data_1);
-        XELOGGPU("  %.4X <- %.8X", reg_index_2, reg_data_2);
+        const char* reg_name_1 = xenos::GetRegisterName(reg_index_1);
+        const char* reg_name_2 = xenos::GetRegisterName(reg_index_2);
+        XELOGGPU("  %.8X -> %.4X %s", reg_data_1, reg_index_1,
+                                      reg_name_1 ? reg_name_1 : "");
+        XELOGGPU("  %.8X -> %.4X %s", reg_data_2, reg_index_2,
+                                      reg_name_2 ? reg_name_2 : "");
         // TODO(benvanik): process register writes.
         n += 1 + 2;
       }
diff --git a/src/xenia/gpu/xenos/register_table.inc b/src/xenia/gpu/xenos/register_table.inc
new file mode 100644
index 000000000..ebc7d0d70
--- /dev/null
+++ b/src/xenia/gpu/xenos/register_table.inc
@@ -0,0 +1,176 @@
+/**
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2013 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+// This is a partial file designed to be included by other files when
+// constructing various tables.
+
+// Almost all of these values are taken directly from:
+// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h
+
+//#define XE_GPU_REGISTER(index, type, name)
+
+XE_GPU_REGISTER(0x01DD,  dword, SCRATCH_ADDR)
+XE_GPU_REGISTER(0x01DC,  dword, SCRATCH_UMSK)
+
+XE_GPU_REGISTER(0x0578,  dword, SCRATCH_REG0)
+XE_GPU_REGISTER(0x0579,  dword, SCRATCH_REG1)
+XE_GPU_REGISTER(0x057A,  dword, SCRATCH_REG2)
+XE_GPU_REGISTER(0x057B,  dword, SCRATCH_REG3)
+XE_GPU_REGISTER(0x057C,  dword, SCRATCH_REG4)
+XE_GPU_REGISTER(0x057D,  dword, SCRATCH_REG5)
+XE_GPU_REGISTER(0x057E,  dword, SCRATCH_REG6)
+XE_GPU_REGISTER(0x057F,  dword, SCRATCH_REG7)
+
+XE_GPU_REGISTER(0x05C8,  dword, WAIT_UNTIL)
+
+XE_GPU_REGISTER(0x0A02,  dword, UNKNOWN_0A02)
+XE_GPU_REGISTER(0x0A03,  dword, UNKNOWN_0A03)
+XE_GPU_REGISTER(0x0A04,  dword, UNKNOWN_0A04)
+XE_GPU_REGISTER(0x0A05,  dword, UNKNOWN_0A05)
+
+XE_GPU_REGISTER(0x0A2F,  dword, COHER_SIZE_HOST)
+XE_GPU_REGISTER(0x0A30,  dword, COHER_BASE_HOST)
+XE_GPU_REGISTER(0x0A31,  dword, COHER_STATUS_HOST)
+
+XE_GPU_REGISTER(0x0D01,  dword, SQ_FLOW_CONTROL)
+XE_GPU_REGISTER(0x0D02,  dword, SQ_INST_STORE_MANAGMENT)
+XE_GPU_REGISTER(0x0D04,  dword, SQ_EO_RT)
+
+XE_GPU_REGISTER(0x0C85,  dword, PA_CL_ENHANCE)
+
+XE_GPU_REGISTER(0x0E42,  dword, UNKNOWN_0E42)
+
+XE_GPU_REGISTER(0x0F01,  dword, RB_BC_CONTROL)
+
+XE_GPU_REGISTER(0x200D,  dword, COHER_DEST_BASE_7)
+
+XE_GPU_REGISTER(0x2080,  dword, PA_SC_WINDOW_OFFSET)
+XE_GPU_REGISTER(0x2081,  dword, PA_SC_WINDOW_SCISSOR_TL)
+XE_GPU_REGISTER(0x2082,  dword, PA_SC_WINDOW_SCISSOR_BR)
+
+XE_GPU_REGISTER(0x2100,  dword, VGT_MAX_VTX_INDX)
+XE_GPU_REGISTER(0x2101,  dword, VGT_MIN_VTX_INDX)
+XE_GPU_REGISTER(0x2102,  dword, VGT_INDX_OFFSET)
+XE_GPU_REGISTER(0x2103,  dword, VGT_MULTI_PRIM_IB_RESET_INDX)
+XE_GPU_REGISTER(0x2104,  dword, RB_COLOR_MASK)
+XE_GPU_REGISTER(0x2105,  float, RB_BLEND_RED)
+XE_GPU_REGISTER(0x2106,  float, RB_BLEND_GREEN)
+XE_GPU_REGISTER(0x2107,  float, RB_BLEND_BLUE)
+XE_GPU_REGISTER(0x2108,  float, RB_BLEND_ALPHA)
+XE_GPU_REGISTER(0x2109,  float, RB_FOG_COLOR_RED)
+XE_GPU_REGISTER(0x210A,  float, RB_FOG_COLOR_GREEN)
+XE_GPU_REGISTER(0x210B,  float, RB_FOG_COLOR_BLUE)
+XE_GPU_REGISTER(0x210C,  dword, RB_STENCILREFMASK_BF)
+XE_GPU_REGISTER(0x210D,  dword, RB_STENCILREFMASK)
+XE_GPU_REGISTER(0x210E,  float, RB_ALPHA_REF)
+XE_GPU_REGISTER(0x210F,  float, PA_CL_VPORT_XSCALE)
+XE_GPU_REGISTER(0x2110,  float, PA_CL_VPORT_XOFFSET)
+XE_GPU_REGISTER(0x2111,  float, PA_CL_VPORT_YSCALE)
+XE_GPU_REGISTER(0x2112,  float, PA_CL_VPORT_YOFFSET)
+XE_GPU_REGISTER(0x2113,  float, PA_CL_VPORT_ZSCALE)
+XE_GPU_REGISTER(0x2114,  float, PA_CL_VPORT_ZOFFSET)
+
+XE_GPU_REGISTER(0x2180,  dword, SQ_PROGRAM_CNTL)
+XE_GPU_REGISTER(0x2181,  dword, SQ_CONTEXT_MISC)
+XE_GPU_REGISTER(0x2182,  dword, SQ_INTERPOLATOR_CNTL)
+XE_GPU_REGISTER(0x2183,  dword, SQ_WRAPPING_0)
+XE_GPU_REGISTER(0x2184,  dword, SQ_WRAPPING_1)
+
+XE_GPU_REGISTER(0x2200,  dword, RB_DEPTHCONTROL)
+XE_GPU_REGISTER(0x2201,  dword, RB_BLENDCONTROL_0)
+XE_GPU_REGISTER(0x2202,  dword, RB_COLORCONTROL)
+XE_GPU_REGISTER(0x2203,  dword, VGT_CURRENT_BIN_ID_MAX)
+XE_GPU_REGISTER(0x2204,  dword, PA_CL_CLIP_CNTL)
+XE_GPU_REGISTER(0x2205,  dword, PA_SU_SC_MODE_CNTL)
+XE_GPU_REGISTER(0x2206,  dword, PA_CL_VTE_CNTL)
+XE_GPU_REGISTER(0x2207,  dword, VGT_CURRENT_BIN_ID_MIN)
+XE_GPU_REGISTER(0x2208,  dword, RB_MODECONTROL)
+XE_GPU_REGISTER(0x2209,  dword, RB_BLENDCONTROL_1)
+XE_GPU_REGISTER(0x220A,  dword, RB_BLENDCONTROL_2)
+XE_GPU_REGISTER(0x220B,  dword, RB_BLENDCONTROL_3)
+
+XE_GPU_REGISTER(0x2280,  dword, PA_SU_POINT_SIZE)
+XE_GPU_REGISTER(0x2281,  dword, PA_SU_POINT_MINMAX)
+XE_GPU_REGISTER(0x2282,  dword, PA_SU_LINE_CNTL)
+XE_GPU_REGISTER(0x2283,  dword, PA_SC_LINE_STIPPLE)
+XE_GPU_REGISTER(0x2284,  dword, UNKNOWN_2284)
+XE_GPU_REGISTER(0x2285,  dword, UNKNOWN_2285)
+XE_GPU_REGISTER(0x2286,  float, UNKNOWN_2286)
+XE_GPU_REGISTER(0x2287,  float, UNKNOWN_2287)
+XE_GPU_REGISTER(0x2288,  dword, UNKNOWN_2288)
+XE_GPU_REGISTER(0x2289,  dword, UNKNOWN_2289)
+XE_GPU_REGISTER(0x228A,  dword, UNKNOWN_228A)
+XE_GPU_REGISTER(0x228B,  dword, UNKNOWN_228B)
+XE_GPU_REGISTER(0x228C,  dword, UNKNOWN_228C)
+XE_GPU_REGISTER(0x228D,  dword, UNKNOWN_228D)
+XE_GPU_REGISTER(0x228E,  dword, UNKNOWN_228E)
+XE_GPU_REGISTER(0x228F,  dword, UNKNOWN_228F)
+XE_GPU_REGISTER(0x2290,  dword, UNKNOWN_2290)
+XE_GPU_REGISTER(0x2291,  dword, UNKNOWN_2291)
+XE_GPU_REGISTER(0x2292,  dword, UNKNOWN_2292)
+XE_GPU_REGISTER(0x2293,  dword, PA_SC_VIZ_QUERY)
+XE_GPU_REGISTER(0x2294,  dword, VGT_ENHANCE)
+
+XE_GPU_REGISTER(0x2300,  dword, PA_SC_LINE_CNTL)
+XE_GPU_REGISTER(0x2301,  dword, PA_SC_AA_CONFIG)
+XE_GPU_REGISTER(0x2302,  dword, PA_SU_VTX_CNTL)
+XE_GPU_REGISTER(0x2303,  float, PA_CL_GB_VERT_CLIP_ADJ)
+XE_GPU_REGISTER(0x2304,  float, PA_CL_GB_VERT_DISC_ADJ)
+XE_GPU_REGISTER(0x2305,  float, PA_CL_GB_HORZ_CLIP_ADJ)
+XE_GPU_REGISTER(0x2306,  float, PA_CL_GB_HORZ_DISC_ADJ)
+XE_GPU_REGISTER(0x2307,  dword, SQ_VS_CONST)
+XE_GPU_REGISTER(0x2308,  dword, SQ_PS_CONST)
+XE_GPU_REGISTER(0x2309,  dword, SQ_DEBUG_MISC_0)
+XE_GPU_REGISTER(0x230A,  dword, SQ_DEBUG_MISC_1)
+XE_GPU_REGISTER(0x230B,  dword, UNKNOWN_230B)
+XE_GPU_REGISTER(0x230C,  dword, UNKNOWN_230C)
+XE_GPU_REGISTER(0x230D,  dword, UNKNOWN_230D)
+XE_GPU_REGISTER(0x230E,  dword, UNKNOWN_230E)
+XE_GPU_REGISTER(0x230F,  dword, UNKNOWN_230F)
+XE_GPU_REGISTER(0x2310,  dword, UNKNOWN_2310)
+XE_GPU_REGISTER(0x2311,  dword, UNKNOWN_2311)
+XE_GPU_REGISTER(0x2312,  dword, PA_SC_AA_MASK)
+XE_GPU_REGISTER(0x2313,  dword, UNKNOWN_2313)
+XE_GPU_REGISTER(0x2314,  dword, UNKNOWN_2314)
+XE_GPU_REGISTER(0x2315,  dword, SQ_CF_PROGRAM_SIZE)
+XE_GPU_REGISTER(0x2316,  dword, VGT_VERTEX_REUSE_BLOCK_CNTL)
+XE_GPU_REGISTER(0x2317,  dword, VGT_OUT_DEALLOC_CNTL)
+XE_GPU_REGISTER(0x2318,  dword, RB_COPY_CONTROL)
+XE_GPU_REGISTER(0x2319,  dword, RB_COPY_DEST_BASE)
+XE_GPU_REGISTER(0x231A,  dword, RB_COPY_DEST_PITCH)
+XE_GPU_REGISTER(0x231B,  dword, RB_COPY_DEST_INFO)
+XE_GPU_REGISTER(0x231C,  dword, RB_HI_CLEAR)
+XE_GPU_REGISTER(0x231D,  dword, RB_DEPTH_CLEAR)
+XE_GPU_REGISTER(0x231E,  dword, RB_COLOR_CLEAR)
+XE_GPU_REGISTER(0x231F,  dword, RB_COLOR_CLEAR_LOW)
+XE_GPU_REGISTER(0x2320,  dword, UNKNOWN_2320)
+XE_GPU_REGISTER(0x2321,  dword, UNKNOWN_2321)
+XE_GPU_REGISTER(0x2322,  dword, UNKNOWN_2322)
+XE_GPU_REGISTER(0x2323,  dword, UNKNOWN_2323)
+XE_GPU_REGISTER(0x2324,  dword, RB_SAMPLE_COUNT_CTL)
+XE_GPU_REGISTER(0x2325,  dword, RB_SAMPLE_COUNT_ADDR)
+
+XE_GPU_REGISTER(0x2380,  float, PA_SU_POLY_OFFSET_FRONT_SCALE)
+XE_GPU_REGISTER(0x2381,  float, PA_SU_POLY_OFFSET_FRONT_OFFSET)
+XE_GPU_REGISTER(0x2382,  float, PA_SU_POLY_OFFSET_BACK_SCALE)
+XE_GPU_REGISTER(0x2383,  float, PA_SU_POLY_OFFSET_BACK_OFFSET)
+XE_GPU_REGISTER(0x2384,  float, UNKNOWN_2384)
+XE_GPU_REGISTER(0x2385,  float, UNKNOWN_2385)
+XE_GPU_REGISTER(0x2386,  float, UNKNOWN_2386)
+XE_GPU_REGISTER(0x2387,  float, UNKNOWN_2387)
+
+// Ignored because I have no clue what these are.
+// XE_GPU_REGISTER(0x8D00,  dword, UNKNOWN_8D00)
+// XE_GPU_REGISTER(0x8D01,  dword, UNKNOWN_8D01)
+// XE_GPU_REGISTER(0x8D02,  dword, UNKNOWN_8D02)
+// XE_GPU_REGISTER(0x8D03,  dword, UNKNOWN_8D03)
+// XE_GPU_REGISTER(0x8D04,  dword, UNKNOWN_8D04)
+// XE_GPU_REGISTER(0x8D05,  dword, UNKNOWN_8D05)
+// XE_GPU_REGISTER(0x8D06,  dword, UNKNOWN_8D06)
+// XE_GPU_REGISTER(0x8D07,  dword, UNKNOWN_8D07)
diff --git a/src/xenia/gpu/xenos/registers.cc b/src/xenia/gpu/xenos/registers.cc
new file mode 100644
index 000000000..5d4e99106
--- /dev/null
+++ b/src/xenia/gpu/xenos/registers.cc
@@ -0,0 +1,27 @@
+/**
+ ******************************************************************************
+ * Xenia : Xbox 360 Emulator Research Project                                 *
+ ******************************************************************************
+ * Copyright 2013 Ben Vanik. All rights reserved.                             *
+ * Released under the BSD license - see LICENSE in the root for more details. *
+ ******************************************************************************
+ */
+
+#include <xenia/gpu/xenos/registers.h>
+
+
+using namespace xe;
+using namespace xe::gpu;
+using namespace xe::gpu::xenos;
+
+
+const char* xe::gpu::xenos::GetRegisterName(uint32_t index) {
+  switch (index) {
+#define XE_GPU_REGISTER(index, type, name) \
+    case index: return #name;
+#include <xenia/gpu/xenos/register_table.inc>
+#undef XE_GPU_REGISTER
+    default:
+      return NULL;
+  }
+}
diff --git a/src/xenia/gpu/xenos/registers.h b/src/xenia/gpu/xenos/registers.h
index 00e38fc0c..84d1e0706 100644
--- a/src/xenia/gpu/xenos/registers.h
+++ b/src/xenia/gpu/xenos/registers.h
@@ -18,15 +18,28 @@ namespace gpu {
 namespace xenos {
 
 
+static const uint32_t kXEGpuRegisterCount = 0x3000;
+
+
+enum Registers {
+#define XE_GPU_REGISTER(index, type, name) \
+    XE_GPU_REG_##name = index,
+#include <xenia/gpu/xenos/register_table.inc>
+#undef XE_GPU_REGISTER
+};
+
+
+const char* GetRegisterName(uint32_t index);
+
+
 union RegisterValue {
-  uint32_t  uint_value;
+  uint32_t  dword_value;
   float     float_value;
 };
 
 
 struct RegisterFile {
-  // TODO(benvanik): figure out the actual number.
-  RegisterValue   registers[0xFFFF];
+  RegisterValue   registers[kXEGpuRegisterCount];
 };
 
 
diff --git a/src/xenia/gpu/xenos/sources.gypi b/src/xenia/gpu/xenos/sources.gypi
index c7f29b01e..b0bc17396 100644
--- a/src/xenia/gpu/xenos/sources.gypi
+++ b/src/xenia/gpu/xenos/sources.gypi
@@ -2,6 +2,7 @@
 {
   'sources': [
     'packets.h',
+    'registers.cc',
     'registers.h',
   ],
 }