add tests.
This commit is contained in:
Ben Vanik
parent
9690525abc
commit
6ce5fa2c48
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@ -56,6 +56,7 @@ XEEMITTER(addcx, 0x7C000014, XO)(PPCHIRBuilder& f, InstrData& i) {
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XEEMITTER(addex, 0x7C000114, XO)(PPCHIRBuilder& f, InstrData& i) {
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// RD <- (RA) + (RB) + XER[CA]
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// CA <- carry bit
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Value* v = f.AddWithCarry(f.LoadGPR(i.XO.RA), f.LoadGPR(i.XO.RB), f.LoadCA(),
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ARITHMETIC_SET_CARRY);
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f.StoreCA(f.DidCarry(v));
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@ -86,6 +87,7 @@ XEEMITTER(addi, 0x38000000, D)(PPCHIRBuilder& f, InstrData& i) {
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XEEMITTER(addic, 0x30000000, D)(PPCHIRBuilder& f, InstrData& i) {
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// RT <- (RA) + EXTS(SI)
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// CA <- carry bit
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Value* v = f.Add(f.LoadGPR(i.D.RA), f.LoadConstant(XEEXTS16(i.D.DS)),
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ARITHMETIC_SET_CARRY);
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f.StoreCA(f.DidCarry(v));
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@ -95,6 +97,7 @@ XEEMITTER(addic, 0x30000000, D)(PPCHIRBuilder& f, InstrData& i) {
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XEEMITTER(addicx, 0x34000000, D)(PPCHIRBuilder& f, InstrData& i) {
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// RT <- (RA) + EXTS(SI)
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// CA <- carry bit
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Value* v = f.Add(f.LoadGPR(i.D.RA), f.LoadConstant(XEEXTS16(i.D.DS)),
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ARITHMETIC_SET_CARRY);
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f.StoreCA(f.DidCarry(v));
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@ -119,6 +122,7 @@ XEEMITTER(addis, 0x3C000000, D)(PPCHIRBuilder& f, InstrData& i) {
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XEEMITTER(addmex, 0x7C0001D4, XO)(PPCHIRBuilder& f, InstrData& i) {
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// RT <- (RA) + CA - 1
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// CA <- carry bit
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Value* v = f.AddWithCarry(f.LoadGPR(i.XO.RA), f.LoadConstant((int64_t)-1),
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f.LoadCA(), ARITHMETIC_SET_CARRY);
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if (i.XO.OE) {
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@ -138,6 +142,7 @@ XEEMITTER(addmex, 0x7C0001D4, XO)(PPCHIRBuilder& f, InstrData& i) {
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XEEMITTER(addzex, 0x7C000194, XO)(PPCHIRBuilder& f, InstrData& i) {
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// RT <- (RA) + CA
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// CA <- carry bit
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Value* v = f.AddWithCarry(f.LoadGPR(i.XO.RA), f.LoadZero(INT64_TYPE),
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f.LoadCA(), ARITHMETIC_SET_CARRY);
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if (i.XO.OE) {
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Binary file not shown.
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@ -0,0 +1,30 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addc.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_addc_1>:
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100000: 7c 64 28 14 addc r3,r4,r5
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_addc_2>:
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10000c: 7c 64 28 14 addc r3,r4,r5
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100010: 7c c0 01 14 adde r6,r0,r0
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100014: 4e 80 00 20 blr
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0000000000100018 <test_addc_3>:
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100018: 7c 64 28 14 addc r3,r4,r5
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_addc_4>:
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100024: 7c 64 28 14 addc r3,r4,r5
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_addc_5>:
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100030: 7c 64 28 14 addc r3,r4,r5
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100034: 7c c0 01 14 adde r6,r0,r0
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100038: 4e 80 00 20 blr
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@ -0,0 +1,5 @@
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0000000000000000 t test_addc_1
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000000000000000c t test_addc_2
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0000000000000018 t test_addc_3
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0000000000000024 t test_addc_4
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0000000000000030 t test_addc_5
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Binary file not shown.
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@ -0,0 +1,70 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_adde.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_adde_1>:
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100000: 7c 64 29 14 adde r3,r4,r5
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_adde_2>:
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10000c: 7c 63 1a 78 xor r3,r3,r3
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100010: 7c 63 18 f8 not r3,r3
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100014: 30 63 00 01 addic r3,r3,1
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100018: 7c 64 29 14 adde r3,r4,r5
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_adde_3>:
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100024: 7c 64 29 14 adde r3,r4,r5
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_adde_4>:
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100030: 7c 63 1a 78 xor r3,r3,r3
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100034: 7c 63 18 f8 not r3,r3
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100038: 30 63 00 01 addic r3,r3,1
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10003c: 7c 64 29 14 adde r3,r4,r5
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100040: 7c c0 01 14 adde r6,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_adde_5>:
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100048: 7c 64 29 14 adde r3,r4,r5
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10004c: 7c c0 01 14 adde r6,r0,r0
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100050: 4e 80 00 20 blr
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0000000000100054 <test_adde_6>:
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100054: 7c 63 1a 78 xor r3,r3,r3
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100058: 7c 63 18 f8 not r3,r3
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10005c: 30 63 00 01 addic r3,r3,1
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100060: 7c 64 29 14 adde r3,r4,r5
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100064: 7c c0 01 14 adde r6,r0,r0
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100068: 4e 80 00 20 blr
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000000000010006c <test_adde_7>:
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10006c: 7c 64 29 14 adde r3,r4,r5
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100070: 7c c0 01 14 adde r6,r0,r0
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100074: 4e 80 00 20 blr
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0000000000100078 <test_adde_8>:
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100078: 7c 63 1a 78 xor r3,r3,r3
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10007c: 7c 63 18 f8 not r3,r3
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100080: 30 63 00 01 addic r3,r3,1
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100084: 7c 64 29 14 adde r3,r4,r5
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100088: 7c c0 01 14 adde r6,r0,r0
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10008c: 4e 80 00 20 blr
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0000000000100090 <test_adde_9>:
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100090: 7c 64 29 14 adde r3,r4,r5
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100094: 7c c0 01 14 adde r6,r0,r0
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100098: 4e 80 00 20 blr
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000000000010009c <test_adde_10>:
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10009c: 7c 63 1a 78 xor r3,r3,r3
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1000a0: 7c 63 18 f8 not r3,r3
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1000a4: 30 63 00 01 addic r3,r3,1
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1000a8: 7c 64 29 14 adde r3,r4,r5
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1000ac: 7c c0 01 14 adde r6,r0,r0
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1000b0: 4e 80 00 20 blr
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@ -0,0 +1,10 @@
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0000000000000000 t test_adde_1
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000000000000000c t test_adde_2
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0000000000000024 t test_adde_3
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0000000000000030 t test_adde_4
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0000000000000048 t test_adde_5
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0000000000000054 t test_adde_6
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000000000000006c t test_adde_7
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0000000000000078 t test_adde_8
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0000000000000090 t test_adde_9
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000000000000009c t test_adde_10
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Binary file not shown.
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@ -0,0 +1,57 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addme.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_addme_1>:
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100000: 7c 64 01 d4 addme r3,r4
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_addme_2>:
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10000c: 7c 63 1a 78 xor r3,r3,r3
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100010: 7c 63 18 f8 not r3,r3
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100014: 30 63 00 01 addic r3,r3,1
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100018: 7c 64 01 d4 addme r3,r4
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_addme_3>:
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100024: 7c 64 01 d4 addme r3,r4
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_addme_4>:
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100030: 7c 63 1a 78 xor r3,r3,r3
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100034: 7c 63 18 f8 not r3,r3
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100038: 30 63 00 01 addic r3,r3,1
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10003c: 7c 64 01 d4 addme r3,r4
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100040: 7c c0 01 14 adde r6,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_addme_5>:
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100048: 7c 64 01 d4 addme r3,r4
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10004c: 7c c0 01 14 adde r6,r0,r0
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100050: 4e 80 00 20 blr
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0000000000100054 <test_addme_6>:
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100054: 7c 63 1a 78 xor r3,r3,r3
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100058: 7c 63 18 f8 not r3,r3
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10005c: 30 63 00 01 addic r3,r3,1
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100060: 7c 64 01 d4 addme r3,r4
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100064: 7c c0 01 14 adde r6,r0,r0
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100068: 4e 80 00 20 blr
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000000000010006c <test_addme_7>:
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10006c: 7c 64 01 d4 addme r3,r4
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100070: 7c c0 01 14 adde r6,r0,r0
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100074: 4e 80 00 20 blr
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0000000000100078 <test_addme_8>:
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100078: 7c 63 1a 78 xor r3,r3,r3
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10007c: 7c 63 18 f8 not r3,r3
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100080: 30 63 00 01 addic r3,r3,1
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100084: 7c 64 01 d4 addme r3,r4
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100088: 7c c0 01 14 adde r6,r0,r0
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10008c: 4e 80 00 20 blr
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@ -0,0 +1,8 @@
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0000000000000000 t test_addme_1
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000000000000000c t test_addme_2
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0000000000000024 t test_addme_3
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0000000000000030 t test_addme_4
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0000000000000048 t test_addme_5
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0000000000000054 t test_addme_6
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000000000000006c t test_addme_7
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0000000000000078 t test_addme_8
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Binary file not shown.
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@ -0,0 +1,57 @@
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/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addze.o: file format elf64-powerpc
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Disassembly of section .text:
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0000000000100000 <test_addze_1>:
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100000: 7c 64 01 94 addze r3,r4
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100004: 7c c0 01 14 adde r6,r0,r0
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100008: 4e 80 00 20 blr
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000000000010000c <test_addze_2>:
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10000c: 7c 63 1a 78 xor r3,r3,r3
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100010: 7c 63 18 f8 not r3,r3
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100014: 30 63 00 01 addic r3,r3,1
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100018: 7c 64 01 94 addze r3,r4
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10001c: 7c c0 01 14 adde r6,r0,r0
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100020: 4e 80 00 20 blr
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0000000000100024 <test_addze_3>:
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100024: 7c 64 01 94 addze r3,r4
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100028: 7c c0 01 14 adde r6,r0,r0
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10002c: 4e 80 00 20 blr
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0000000000100030 <test_addze_4>:
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100030: 7c 63 1a 78 xor r3,r3,r3
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100034: 7c 63 18 f8 not r3,r3
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100038: 30 63 00 01 addic r3,r3,1
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10003c: 7c 64 01 94 addze r3,r4
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100040: 7c c0 01 14 adde r6,r0,r0
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100044: 4e 80 00 20 blr
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0000000000100048 <test_addze_5>:
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100048: 7c 64 01 94 addze r3,r4
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10004c: 7c c0 01 14 adde r6,r0,r0
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100050: 4e 80 00 20 blr
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0000000000100054 <test_addze_6>:
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100054: 7c 63 1a 78 xor r3,r3,r3
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100058: 7c 63 18 f8 not r3,r3
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10005c: 30 63 00 01 addic r3,r3,1
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100060: 7c 64 01 94 addze r3,r4
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100064: 7c c0 01 14 adde r6,r0,r0
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100068: 4e 80 00 20 blr
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000000000010006c <test_addze_7>:
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10006c: 7c 64 01 94 addze r3,r4
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100070: 7c c0 01 14 adde r6,r0,r0
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100074: 4e 80 00 20 blr
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0000000000100078 <test_addze_8>:
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100078: 7c 63 1a 78 xor r3,r3,r3
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10007c: 7c 63 18 f8 not r3,r3
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100080: 30 63 00 01 addic r3,r3,1
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100084: 7c 64 01 94 addze r3,r4
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100088: 7c c0 01 14 adde r6,r0,r0
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10008c: 4e 80 00 20 blr
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@ -0,0 +1,8 @@
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0000000000000000 t test_addze_1
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000000000000000c t test_addze_2
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0000000000000024 t test_addze_3
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0000000000000030 t test_addze_4
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0000000000000048 t test_addze_5
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0000000000000054 t test_addze_6
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000000000000006c t test_addze_7
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0000000000000078 t test_addze_8
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@ -0,0 +1,54 @@
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test_addc_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_addc_2:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_addc_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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#_ REGISTER_OUT r6 1
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test_addc_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 123
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x000000000000007A
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 123
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#_ REGISTER_OUT r6 1
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test_addc_5:
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#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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addc r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
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#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r6 1
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test_adde_1:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 3
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_2:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 2
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 4
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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#_ REGISTER_OUT r6 0
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test_adde_3:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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adde r3, r4, r5
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adde r6, r0, r0
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blr
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#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0
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#_ REGISTER_OUT r6 0
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test_adde_4:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0
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xor r3, r3, r3
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not r3, r3
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addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_7:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 123
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x000000000000007A
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 123
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_8:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 123
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x000000000000007B
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 123
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_9:
|
||||
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
|
||||
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_adde_10:
|
||||
#_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
adde r3, r4, r5
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
test_addme_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_2:
|
||||
#_ REGISTER_IN r4 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_3:
|
||||
#_ REGISTER_IN r4 12
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 11
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_4:
|
||||
#_ REGISTER_IN r4 12
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 12
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addme_7:
|
||||
#_ REGISTER_IN r4 0
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addme_8:
|
||||
#_ REGISTER_IN r4 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addme r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
test_addze_1:
|
||||
#_ REGISTER_IN r4 1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_2:
|
||||
#_ REGISTER_IN r4 1
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 2
|
||||
#_ REGISTER_OUT r4 1
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_3:
|
||||
#_ REGISTER_IN r4 12
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 12
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_4:
|
||||
#_ REGISTER_IN r4 12
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 13
|
||||
#_ REGISTER_OUT r4 12
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_5:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_6:
|
||||
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
|
||||
#_ REGISTER_OUT r6 1
|
||||
|
||||
test_addze_7:
|
||||
#_ REGISTER_IN r4 0
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 0
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
|
||||
test_addze_8:
|
||||
#_ REGISTER_IN r4 0
|
||||
xor r3, r3, r3
|
||||
not r3, r3
|
||||
addic r3, r3, 1 # CA=1
|
||||
addze r3, r4
|
||||
adde r6, r0, r0
|
||||
blr
|
||||
#_ REGISTER_OUT r3 1
|
||||
#_ REGISTER_OUT r4 0
|
||||
#_ REGISTER_OUT r6 0
|
||||
Loading…
Reference in New Issue