From 6ce5fa2c482c4df309c5f6022a40be6e19a13d62 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sat, 13 Sep 2014 01:04:53 -0700 Subject: [PATCH] add tests. --- src/alloy/frontend/ppc/ppc_emit_alu.cc | 5 + .../frontend/ppc/test/bin/instr_addc.bin | Bin 0 -> 60 bytes .../frontend/ppc/test/bin/instr_addc.dis | 30 +++++ .../frontend/ppc/test/bin/instr_addc.map | 5 + .../frontend/ppc/test/bin/instr_adde.bin | Bin 0 -> 180 bytes .../frontend/ppc/test/bin/instr_adde.dis | 70 ++++++++++ .../frontend/ppc/test/bin/instr_adde.map | 10 ++ .../frontend/ppc/test/bin/instr_addme.bin | Bin 0 -> 144 bytes .../frontend/ppc/test/bin/instr_addme.dis | 57 ++++++++ .../frontend/ppc/test/bin/instr_addme.map | 8 ++ .../frontend/ppc/test/bin/instr_addze.bin | Bin 0 -> 144 bytes .../frontend/ppc/test/bin/instr_addze.dis | 57 ++++++++ .../frontend/ppc/test/bin/instr_addze.map | 8 ++ src/alloy/frontend/ppc/test/instr_addc.s | 54 ++++++++ src/alloy/frontend/ppc/test/instr_adde.s | 124 ++++++++++++++++++ src/alloy/frontend/ppc/test/instr_addme.s | 83 ++++++++++++ src/alloy/frontend/ppc/test/instr_addze.s | 83 ++++++++++++ 17 files changed, 594 insertions(+) create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addc.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addc.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addc.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_adde.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_adde.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_adde.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addme.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addme.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addme.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addze.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addze.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_addze.map create mode 100644 src/alloy/frontend/ppc/test/instr_addc.s create mode 100644 src/alloy/frontend/ppc/test/instr_adde.s create mode 100644 src/alloy/frontend/ppc/test/instr_addme.s create mode 100644 src/alloy/frontend/ppc/test/instr_addze.s diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc index 8d03e4640..17a3863f9 100644 --- a/src/alloy/frontend/ppc/ppc_emit_alu.cc +++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc @@ -56,6 +56,7 @@ XEEMITTER(addcx, 0x7C000014, XO)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(addex, 0x7C000114, XO)(PPCHIRBuilder& f, InstrData& i) { // RD <- (RA) + (RB) + XER[CA] + // CA <- carry bit Value* v = f.AddWithCarry(f.LoadGPR(i.XO.RA), f.LoadGPR(i.XO.RB), f.LoadCA(), ARITHMETIC_SET_CARRY); f.StoreCA(f.DidCarry(v)); @@ -86,6 +87,7 @@ XEEMITTER(addi, 0x38000000, D)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(addic, 0x30000000, D)(PPCHIRBuilder& f, InstrData& i) { // RT <- (RA) + EXTS(SI) + // CA <- carry bit Value* v = f.Add(f.LoadGPR(i.D.RA), f.LoadConstant(XEEXTS16(i.D.DS)), ARITHMETIC_SET_CARRY); f.StoreCA(f.DidCarry(v)); @@ -95,6 +97,7 @@ XEEMITTER(addic, 0x30000000, D)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(addicx, 0x34000000, D)(PPCHIRBuilder& f, InstrData& i) { // RT <- (RA) + EXTS(SI) + // CA <- carry bit Value* v = f.Add(f.LoadGPR(i.D.RA), f.LoadConstant(XEEXTS16(i.D.DS)), ARITHMETIC_SET_CARRY); f.StoreCA(f.DidCarry(v)); @@ -119,6 +122,7 @@ XEEMITTER(addis, 0x3C000000, D)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(addmex, 0x7C0001D4, XO)(PPCHIRBuilder& f, InstrData& i) { // RT <- (RA) + CA - 1 + // CA <- carry bit Value* v = f.AddWithCarry(f.LoadGPR(i.XO.RA), f.LoadConstant((int64_t)-1), f.LoadCA(), ARITHMETIC_SET_CARRY); if (i.XO.OE) { @@ -138,6 +142,7 @@ XEEMITTER(addmex, 0x7C0001D4, XO)(PPCHIRBuilder& f, InstrData& i) { XEEMITTER(addzex, 0x7C000194, XO)(PPCHIRBuilder& f, InstrData& i) { // RT <- (RA) + CA + // CA <- carry bit Value* v = f.AddWithCarry(f.LoadGPR(i.XO.RA), f.LoadZero(INT64_TYPE), f.LoadCA(), ARITHMETIC_SET_CARRY); if (i.XO.OE) { diff --git a/src/alloy/frontend/ppc/test/bin/instr_addc.bin b/src/alloy/frontend/ppc/test/bin/instr_addc.bin new file mode 100644 index 0000000000000000000000000000000000000000..49641167a1cf4301cc879d44b56694f9af2d8357 GIT binary patch literal 60 Wcmb%n--` literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_addc.dis b/src/alloy/frontend/ppc/test/bin/instr_addc.dis new file mode 100644 index 000000000..035eaa01d --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_addc.dis @@ -0,0 +1,30 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addc.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 64 28 14 addc r3,r4,r5 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 64 28 14 addc r3,r4,r5 + 100010: 7c c0 01 14 adde r6,r0,r0 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 28 14 addc r3,r4,r5 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 64 28 14 addc r3,r4,r5 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 64 28 14 addc r3,r4,r5 + 100034: 7c c0 01 14 adde r6,r0,r0 + 100038: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_addc.map b/src/alloy/frontend/ppc/test/bin/instr_addc.map new file mode 100644 index 000000000..4ec8531ad --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_addc.map @@ -0,0 +1,5 @@ +0000000000000000 t test_addc_1 +000000000000000c t test_addc_2 +0000000000000018 t test_addc_3 +0000000000000024 t test_addc_4 +0000000000000030 t test_addc_5 diff --git a/src/alloy/frontend/ppc/test/bin/instr_adde.bin b/src/alloy/frontend/ppc/test/bin/instr_adde.bin new file mode 100644 index 0000000000000000000000000000000000000000..3b467563d788d9f2a8accb729255d78788dd7526 GIT binary patch literal 180 ncmb: + 100000: 7c 64 29 14 adde r3,r4,r5 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 63 1a 78 xor r3,r3,r3 + 100010: 7c 63 18 f8 not r3,r3 + 100014: 30 63 00 01 addic r3,r3,1 + 100018: 7c 64 29 14 adde r3,r4,r5 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 64 29 14 adde r3,r4,r5 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 63 1a 78 xor r3,r3,r3 + 100034: 7c 63 18 f8 not r3,r3 + 100038: 30 63 00 01 addic r3,r3,1 + 10003c: 7c 64 29 14 adde r3,r4,r5 + 100040: 7c c0 01 14 adde r6,r0,r0 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 29 14 adde r3,r4,r5 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 63 1a 78 xor r3,r3,r3 + 100058: 7c 63 18 f8 not r3,r3 + 10005c: 30 63 00 01 addic r3,r3,1 + 100060: 7c 64 29 14 adde r3,r4,r5 + 100064: 7c c0 01 14 adde r6,r0,r0 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 7c 64 29 14 adde r3,r4,r5 + 100070: 7c c0 01 14 adde r6,r0,r0 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 63 1a 78 xor r3,r3,r3 + 10007c: 7c 63 18 f8 not r3,r3 + 100080: 30 63 00 01 addic r3,r3,1 + 100084: 7c 64 29 14 adde r3,r4,r5 + 100088: 7c c0 01 14 adde r6,r0,r0 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 29 14 adde r3,r4,r5 + 100094: 7c c0 01 14 adde r6,r0,r0 + 100098: 4e 80 00 20 blr + +000000000010009c : + 10009c: 7c 63 1a 78 xor r3,r3,r3 + 1000a0: 7c 63 18 f8 not r3,r3 + 1000a4: 30 63 00 01 addic r3,r3,1 + 1000a8: 7c 64 29 14 adde r3,r4,r5 + 1000ac: 7c c0 01 14 adde r6,r0,r0 + 1000b0: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_adde.map b/src/alloy/frontend/ppc/test/bin/instr_adde.map new file mode 100644 index 000000000..aa560c21a --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_adde.map @@ -0,0 +1,10 @@ +0000000000000000 t test_adde_1 +000000000000000c t test_adde_2 +0000000000000024 t test_adde_3 +0000000000000030 t test_adde_4 +0000000000000048 t test_adde_5 +0000000000000054 t test_adde_6 +000000000000006c t test_adde_7 +0000000000000078 t test_adde_8 +0000000000000090 t test_adde_9 +000000000000009c t test_adde_10 diff --git a/src/alloy/frontend/ppc/test/bin/instr_addme.bin b/src/alloy/frontend/ppc/test/bin/instr_addme.bin new file mode 100644 index 0000000000000000000000000000000000000000..c47a75603848f7ebb58907d00080dc767eb26206 GIT binary patch literal 144 mcmblI5G6Q1`vN$rE#%chd<1cXl literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_addme.dis b/src/alloy/frontend/ppc/test/bin/instr_addme.dis new file mode 100644 index 000000000..58c8ef1dc --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_addme.dis @@ -0,0 +1,57 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addme.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 64 01 d4 addme r3,r4 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 63 1a 78 xor r3,r3,r3 + 100010: 7c 63 18 f8 not r3,r3 + 100014: 30 63 00 01 addic r3,r3,1 + 100018: 7c 64 01 d4 addme r3,r4 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 64 01 d4 addme r3,r4 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 63 1a 78 xor r3,r3,r3 + 100034: 7c 63 18 f8 not r3,r3 + 100038: 30 63 00 01 addic r3,r3,1 + 10003c: 7c 64 01 d4 addme r3,r4 + 100040: 7c c0 01 14 adde r6,r0,r0 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 01 d4 addme r3,r4 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 63 1a 78 xor r3,r3,r3 + 100058: 7c 63 18 f8 not r3,r3 + 10005c: 30 63 00 01 addic r3,r3,1 + 100060: 7c 64 01 d4 addme r3,r4 + 100064: 7c c0 01 14 adde r6,r0,r0 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 7c 64 01 d4 addme r3,r4 + 100070: 7c c0 01 14 adde r6,r0,r0 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 63 1a 78 xor r3,r3,r3 + 10007c: 7c 63 18 f8 not r3,r3 + 100080: 30 63 00 01 addic r3,r3,1 + 100084: 7c 64 01 d4 addme r3,r4 + 100088: 7c c0 01 14 adde r6,r0,r0 + 10008c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_addme.map b/src/alloy/frontend/ppc/test/bin/instr_addme.map new file mode 100644 index 000000000..1f9efa1b4 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_addme.map @@ -0,0 +1,8 @@ +0000000000000000 t test_addme_1 +000000000000000c t test_addme_2 +0000000000000024 t test_addme_3 +0000000000000030 t test_addme_4 +0000000000000048 t test_addme_5 +0000000000000054 t test_addme_6 +000000000000006c t test_addme_7 +0000000000000078 t test_addme_8 diff --git a/src/alloy/frontend/ppc/test/bin/instr_addze.bin b/src/alloy/frontend/ppc/test/bin/instr_addze.bin new file mode 100644 index 0000000000000000000000000000000000000000..34b5d022a422f4ea5e63ece0e3bc10eb8d8fadd2 GIT binary patch literal 144 mcmblI5G6Q1`vN$rE#%cfx<1KLj literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_addze.dis b/src/alloy/frontend/ppc/test/bin/instr_addze.dis new file mode 100644 index 000000000..c7b64c89a --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_addze.dis @@ -0,0 +1,57 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_addze.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 64 01 94 addze r3,r4 + 100004: 7c c0 01 14 adde r6,r0,r0 + 100008: 4e 80 00 20 blr + +000000000010000c : + 10000c: 7c 63 1a 78 xor r3,r3,r3 + 100010: 7c 63 18 f8 not r3,r3 + 100014: 30 63 00 01 addic r3,r3,1 + 100018: 7c 64 01 94 addze r3,r4 + 10001c: 7c c0 01 14 adde r6,r0,r0 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 7c 64 01 94 addze r3,r4 + 100028: 7c c0 01 14 adde r6,r0,r0 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 63 1a 78 xor r3,r3,r3 + 100034: 7c 63 18 f8 not r3,r3 + 100038: 30 63 00 01 addic r3,r3,1 + 10003c: 7c 64 01 94 addze r3,r4 + 100040: 7c c0 01 14 adde r6,r0,r0 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 01 94 addze r3,r4 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 63 1a 78 xor r3,r3,r3 + 100058: 7c 63 18 f8 not r3,r3 + 10005c: 30 63 00 01 addic r3,r3,1 + 100060: 7c 64 01 94 addze r3,r4 + 100064: 7c c0 01 14 adde r6,r0,r0 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 7c 64 01 94 addze r3,r4 + 100070: 7c c0 01 14 adde r6,r0,r0 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 63 1a 78 xor r3,r3,r3 + 10007c: 7c 63 18 f8 not r3,r3 + 100080: 30 63 00 01 addic r3,r3,1 + 100084: 7c 64 01 94 addze r3,r4 + 100088: 7c c0 01 14 adde r6,r0,r0 + 10008c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_addze.map b/src/alloy/frontend/ppc/test/bin/instr_addze.map new file mode 100644 index 000000000..99bf605c6 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_addze.map @@ -0,0 +1,8 @@ +0000000000000000 t test_addze_1 +000000000000000c t test_addze_2 +0000000000000024 t test_addze_3 +0000000000000030 t test_addze_4 +0000000000000048 t test_addze_5 +0000000000000054 t test_addze_6 +000000000000006c t test_addze_7 +0000000000000078 t test_addze_8 diff --git a/src/alloy/frontend/ppc/test/instr_addc.s b/src/alloy/frontend/ppc/test/instr_addc.s new file mode 100644 index 000000000..75fa41c7a --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_addc.s @@ -0,0 +1,54 @@ +test_addc_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 2 + addc r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 3 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + #_ REGISTER_OUT r6 0 + +test_addc_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + addc r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + +test_addc_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + addc r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + +test_addc_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 123 + addc r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x000000000000007A + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 123 + #_ REGISTER_OUT r6 1 + +test_addc_5: + #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + addc r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_adde.s b/src/alloy/frontend/ppc/test/instr_adde.s new file mode 100644 index 000000000..d6c93a1f5 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_adde.s @@ -0,0 +1,124 @@ +test_adde_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 2 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 3 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + #_ REGISTER_OUT r6 0 + +test_adde_2: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 2 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 4 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 2 + #_ REGISTER_OUT r6 0 + +test_adde_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 0 + +test_adde_4: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0 + #_ REGISTER_OUT r6 1 + +test_adde_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + +test_adde_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + #_ REGISTER_OUT r6 1 + +test_adde_7: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 123 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x000000000000007A + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 123 + #_ REGISTER_OUT r6 1 + +test_adde_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 123 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x000000000000007B + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 123 + #_ REGISTER_OUT r6 1 + +test_adde_9: + #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_adde_10: + #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + adde r3, r4, r5 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_addme.s b/src/alloy/frontend/ppc/test/instr_addme.s new file mode 100644 index 000000000..afea951b3 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_addme.s @@ -0,0 +1,83 @@ +test_addme_1: + #_ REGISTER_IN r4 1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 1 + +test_addme_2: + #_ REGISTER_IN r4 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 1 + +test_addme_3: + #_ REGISTER_IN r4 12 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 11 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 1 + +test_addme_4: + #_ REGISTER_IN r4 12 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 12 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 1 + +test_addme_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_addme_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_addme_7: + #_ REGISTER_IN r4 0 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 0 + +test_addme_8: + #_ REGISTER_IN r4 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addme r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 1 diff --git a/src/alloy/frontend/ppc/test/instr_addze.s b/src/alloy/frontend/ppc/test/instr_addze.s new file mode 100644 index 000000000..17c4942b9 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_addze.s @@ -0,0 +1,83 @@ +test_addze_1: + #_ REGISTER_IN r4 1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + +test_addze_2: + #_ REGISTER_IN r4 1 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 2 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r6 0 + +test_addze_3: + #_ REGISTER_IN r4 12 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 12 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 0 + +test_addze_4: + #_ REGISTER_IN r4 12 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 13 + #_ REGISTER_OUT r4 12 + #_ REGISTER_OUT r6 0 + +test_addze_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 0 + +test_addze_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r6 1 + +test_addze_7: + #_ REGISTER_IN r4 0 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 0 + +test_addze_8: + #_ REGISTER_IN r4 0 + xor r3, r3, r3 + not r3, r3 + addic r3, r3, 1 # CA=1 + addze r3, r4 + adde r6, r0, r0 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0 + #_ REGISTER_OUT r6 0