mul tests + fix.

This commit is contained in:
Ben Vanik 2014-09-13 12:39:00 -07:00
parent 82102dd390
commit 0d92e14c9f
29 changed files with 703 additions and 2 deletions

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@ -366,8 +366,8 @@ XEEMITTER(mullwx, 0x7C0001D6, XO)(PPCHIRBuilder& f, InstrData& i) {
return 1;
}
Value* v = f.Mul(
f.ZeroExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE),
f.ZeroExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE));
f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE),
f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE));
f.StoreGPR(i.XO.RT, v);
if (i.XO.Rc) {
f.UpdateCR(0, v);

Binary file not shown.

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@ -0,0 +1,25 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulhd.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mulhd_1>:
100000: 7c 64 28 92 mulhd r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mulhd_2>:
100008: 7c 64 28 92 mulhd r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhd_3>:
100010: 7c 64 28 92 mulhd r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mulhd_4>:
100018: 7c 64 28 92 mulhd r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhd_5>:
100020: 7c 64 28 92 mulhd r3,r4,r5
100024: 4e 80 00 20 blr

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@ -0,0 +1,5 @@
0000000000000000 t test_mulhd_1
0000000000000008 t test_mulhd_2
0000000000000010 t test_mulhd_3
0000000000000018 t test_mulhd_4
0000000000000020 t test_mulhd_5

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@ -0,0 +1,25 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulhdu.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mulhdu_1>:
100000: 7c 64 28 12 mulhdu r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mulhdu_2>:
100008: 7c 64 28 12 mulhdu r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhdu_3>:
100010: 7c 64 28 12 mulhdu r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mulhdu_4>:
100018: 7c 64 28 12 mulhdu r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhdu_5>:
100020: 7c 64 28 12 mulhdu r3,r4,r5
100024: 4e 80 00 20 blr

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@ -0,0 +1,5 @@
0000000000000000 t test_mulhdu_1
0000000000000008 t test_mulhdu_2
0000000000000010 t test_mulhdu_3
0000000000000018 t test_mulhdu_4
0000000000000020 t test_mulhdu_5

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@ -0,0 +1,29 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulhw.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mulhw_1>:
100000: 7c 64 28 96 mulhw r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mulhw_2>:
100008: 7c 64 28 96 mulhw r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhw_3>:
100010: 7c 64 28 96 mulhw r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mulhw_4>:
100018: 7c 64 28 96 mulhw r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhw_5>:
100020: 7c 64 28 96 mulhw r3,r4,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_mulhw_6>:
100028: 7c 64 28 96 mulhw r3,r4,r5
10002c: 4e 80 00 20 blr

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@ -0,0 +1,6 @@
0000000000000000 t test_mulhw_1
0000000000000008 t test_mulhw_2
0000000000000010 t test_mulhw_3
0000000000000018 t test_mulhw_4
0000000000000020 t test_mulhw_5
0000000000000028 t test_mulhw_6

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@ -0,0 +1,29 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulhwu.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mulhwu_1>:
100000: 7c 64 28 16 mulhwu r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mulhwu_2>:
100008: 7c 64 28 16 mulhwu r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhwu_3>:
100010: 7c 64 28 16 mulhwu r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mulhwu_4>:
100018: 7c 64 28 16 mulhwu r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhwu_5>:
100020: 7c 64 28 16 mulhwu r3,r4,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_mulhwu_6>:
100028: 7c 64 28 16 mulhwu r3,r4,r5
10002c: 4e 80 00 20 blr

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@ -0,0 +1,6 @@
0000000000000000 t test_mulhwu_1
0000000000000008 t test_mulhwu_2
0000000000000010 t test_mulhwu_3
0000000000000018 t test_mulhwu_4
0000000000000020 t test_mulhwu_5
0000000000000028 t test_mulhwu_6

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@ -0,0 +1,37 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulld.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mulld_1>:
100000: 7c 64 29 d2 mulld r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mulld_2>:
100008: 7c 64 29 d2 mulld r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulld_3>:
100010: 7c 64 29 d2 mulld r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mulld_4>:
100018: 7c 64 29 d2 mulld r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulld_5>:
100020: 7c 64 29 d2 mulld r3,r4,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_mulld_6>:
100028: 7c 64 29 d2 mulld r3,r4,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_mulld_7>:
100030: 7c 64 29 d2 mulld r3,r4,r5
100034: 4e 80 00 20 blr
0000000000100038 <test_mulld_8>:
100038: 7c 64 29 d2 mulld r3,r4,r5
10003c: 4e 80 00 20 blr

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@ -0,0 +1,8 @@
0000000000000000 t test_mulld_1
0000000000000008 t test_mulld_2
0000000000000010 t test_mulld_3
0000000000000018 t test_mulld_4
0000000000000020 t test_mulld_5
0000000000000028 t test_mulld_6
0000000000000030 t test_mulld_7
0000000000000038 t test_mulld_8

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@ -0,0 +1,37 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulli.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mulli_1>:
100000: 1c 64 00 00 mulli r3,r4,0
100004: 4e 80 00 20 blr
0000000000100008 <test_mulli_2>:
100008: 1c 64 00 01 mulli r3,r4,1
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulli_3>:
100010: 1c 64 ff ff mulli r3,r4,-1
100014: 4e 80 00 20 blr
0000000000100018 <test_mulli_4>:
100018: 1c 64 ff ff mulli r3,r4,-1
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulli_5>:
100020: 1c 64 00 01 mulli r3,r4,1
100024: 4e 80 00 20 blr
0000000000100028 <test_mulli_6>:
100028: 1c 64 00 02 mulli r3,r4,2
10002c: 4e 80 00 20 blr
0000000000100030 <test_mulli_7>:
100030: 1c 64 ff ff mulli r3,r4,-1
100034: 4e 80 00 20 blr
0000000000100038 <test_mulli_8>:
100038: 1c 64 ff ff mulli r3,r4,-1
10003c: 4e 80 00 20 blr

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@ -0,0 +1,8 @@
0000000000000000 t test_mulli_1
0000000000000008 t test_mulli_2
0000000000000010 t test_mulli_3
0000000000000018 t test_mulli_4
0000000000000020 t test_mulli_5
0000000000000028 t test_mulli_6
0000000000000030 t test_mulli_7
0000000000000038 t test_mulli_8

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@ -0,0 +1,49 @@
/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mullw.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_mullw_1>:
100000: 7c 64 29 d6 mullw r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mullw_2>:
100008: 7c 64 29 d6 mullw r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mullw_3>:
100010: 7c 64 29 d6 mullw r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mullw_4>:
100018: 7c 64 29 d6 mullw r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mullw_5>:
100020: 7c 64 29 d6 mullw r3,r4,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_mullw_6>:
100028: 7c 64 29 d6 mullw r3,r4,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_mullw_7>:
100030: 7c 64 29 d6 mullw r3,r4,r5
100034: 4e 80 00 20 blr
0000000000100038 <test_mullw_8>:
100038: 7c 64 29 d6 mullw r3,r4,r5
10003c: 4e 80 00 20 blr
0000000000100040 <test_mullw_9>:
100040: 7c 64 29 d6 mullw r3,r4,r5
100044: 4e 80 00 20 blr
0000000000100048 <test_mullw_10>:
100048: 7c 64 29 d6 mullw r3,r4,r5
10004c: 4e 80 00 20 blr
0000000000100050 <test_mullw_11>:
100050: 7c 64 29 d6 mullw r3,r4,r5
100054: 4e 80 00 20 blr

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@ -0,0 +1,11 @@
0000000000000000 t test_mullw_1
0000000000000008 t test_mullw_2
0000000000000010 t test_mullw_3
0000000000000018 t test_mullw_4
0000000000000020 t test_mullw_5
0000000000000028 t test_mullw_6
0000000000000030 t test_mullw_7
0000000000000038 t test_mullw_8
0000000000000040 t test_mullw_9
0000000000000048 t test_mullw_10
0000000000000050 t test_mullw_11

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@ -0,0 +1,44 @@
test_mulhd_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhd_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhd_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhd_4:
#_ REGISTER_IN r4 0x8000000000000000
#_ REGISTER_IN r5 1
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhd_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhd r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

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@ -0,0 +1,44 @@
test_mulhdu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhdu_2:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhdu_3:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulhdu_4:
#_ REGISTER_IN r4 0x8000000000000000
#_ REGISTER_IN r5 1
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x8000000000000000
#_ REGISTER_OUT r5 1
test_mulhdu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhdu r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

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@ -0,0 +1,53 @@
test_mulhw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhw_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

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@ -0,0 +1,53 @@
test_mulhwu_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulhwu_2:
#_ REGISTER_IN r4 0x00000000FFFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000000FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_3:
#_ REGISTER_IN r4 0x00000001FFFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x00000001FFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_4:
#_ REGISTER_IN r4 0x800000007FFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0x800000007FFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulhwu_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
mulhwu r3, r4, r5
blr
#_ REGISTER_OUT r3 0x00000000FFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF

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@ -0,0 +1,72 @@
test_mulld_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mulld_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mulld_3:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_4:
#_ REGISTER_IN r4 123
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mulld_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mulld_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mulld_7:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mulld_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 -1
mulld r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1

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@ -0,0 +1,56 @@
test_mulli_1:
#_ REGISTER_IN r4 1
mulli r3, r4, 0
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
test_mulli_2:
#_ REGISTER_IN r4 1
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
test_mulli_3:
#_ REGISTER_IN r4 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
test_mulli_4:
#_ REGISTER_IN r4 123
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
test_mulli_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, 1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, 2
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
test_mulli_7:
#_ REGISTER_IN r4 1
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
test_mulli_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
mulli r3, r4, -1
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF

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@ -0,0 +1,99 @@
test_mullw_1:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0
test_mullw_2:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 1
test_mullw_3:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_4:
#_ REGISTER_IN r4 123
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 -123
#_ REGISTER_OUT r4 123
#_ REGISTER_OUT r5 -1
test_mullw_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 1
test_mullw_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 2
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 2
test_mullw_7:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 -1
test_mullw_8:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_IN r5 -1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r5 -1
test_mullw_9:
#_ REGISTER_IN r4 0xFFFFFFFF00000000
#_ REGISTER_IN r5 1
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFF00000000
#_ REGISTER_OUT r5 1
test_mullw_10:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0xFFFFFFFF00000000
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0xFFFFFFFF00000000
test_mullw_11:
#_ REGISTER_IN r4 1
#_ REGISTER_IN r5 0x000000007FFFFFFF
mullw r3, r4, r5
blr
#_ REGISTER_OUT r3 0x000000007FFFFFFF
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r5 0x000000007FFFFFFF