From 0d92e14c9f3ad214187e83cf0cd21245a10df483 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sat, 13 Sep 2014 12:39:00 -0700 Subject: [PATCH] mul tests + fix. --- src/alloy/frontend/ppc/ppc_emit_alu.cc | 4 +- .../frontend/ppc/test/bin/instr_mulhd.bin | Bin 0 -> 40 bytes .../frontend/ppc/test/bin/instr_mulhd.dis | 25 +++++ .../frontend/ppc/test/bin/instr_mulhd.map | 5 + .../frontend/ppc/test/bin/instr_mulhdu.bin | Bin 0 -> 40 bytes .../frontend/ppc/test/bin/instr_mulhdu.dis | 25 +++++ .../frontend/ppc/test/bin/instr_mulhdu.map | 5 + .../frontend/ppc/test/bin/instr_mulhw.bin | Bin 0 -> 48 bytes .../frontend/ppc/test/bin/instr_mulhw.dis | 29 +++++ .../frontend/ppc/test/bin/instr_mulhw.map | 6 ++ .../frontend/ppc/test/bin/instr_mulhwu.bin | Bin 0 -> 48 bytes .../frontend/ppc/test/bin/instr_mulhwu.dis | 29 +++++ .../frontend/ppc/test/bin/instr_mulhwu.map | 6 ++ .../frontend/ppc/test/bin/instr_mulld.bin | Bin 0 -> 64 bytes .../frontend/ppc/test/bin/instr_mulld.dis | 37 +++++++ .../frontend/ppc/test/bin/instr_mulld.map | 8 ++ .../frontend/ppc/test/bin/instr_mulli.bin | Bin 0 -> 64 bytes .../frontend/ppc/test/bin/instr_mulli.dis | 37 +++++++ .../frontend/ppc/test/bin/instr_mulli.map | 8 ++ .../frontend/ppc/test/bin/instr_mullw.bin | Bin 0 -> 88 bytes .../frontend/ppc/test/bin/instr_mullw.dis | 49 +++++++++ .../frontend/ppc/test/bin/instr_mullw.map | 11 ++ src/alloy/frontend/ppc/test/instr_mulhd.s | 44 ++++++++ src/alloy/frontend/ppc/test/instr_mulhdu.s | 44 ++++++++ src/alloy/frontend/ppc/test/instr_mulhw.s | 53 ++++++++++ src/alloy/frontend/ppc/test/instr_mulhwu.s | 53 ++++++++++ src/alloy/frontend/ppc/test/instr_mulld.s | 72 +++++++++++++ src/alloy/frontend/ppc/test/instr_mulli.s | 56 ++++++++++ src/alloy/frontend/ppc/test/instr_mullw.s | 99 ++++++++++++++++++ 29 files changed, 703 insertions(+), 2 deletions(-) create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhd.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhd.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhd.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhdu.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhdu.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhdu.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhw.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhw.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhw.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhwu.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhwu.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulhwu.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulld.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulld.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulld.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulli.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulli.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mulli.map create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mullw.bin create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mullw.dis create mode 100644 src/alloy/frontend/ppc/test/bin/instr_mullw.map create mode 100644 src/alloy/frontend/ppc/test/instr_mulhd.s create mode 100644 src/alloy/frontend/ppc/test/instr_mulhdu.s create mode 100644 src/alloy/frontend/ppc/test/instr_mulhw.s create mode 100644 src/alloy/frontend/ppc/test/instr_mulhwu.s create mode 100644 src/alloy/frontend/ppc/test/instr_mulld.s create mode 100644 src/alloy/frontend/ppc/test/instr_mulli.s create mode 100644 src/alloy/frontend/ppc/test/instr_mullw.s diff --git a/src/alloy/frontend/ppc/ppc_emit_alu.cc b/src/alloy/frontend/ppc/ppc_emit_alu.cc index 50095bbb5..93d1b4156 100644 --- a/src/alloy/frontend/ppc/ppc_emit_alu.cc +++ b/src/alloy/frontend/ppc/ppc_emit_alu.cc @@ -366,8 +366,8 @@ XEEMITTER(mullwx, 0x7C0001D6, XO)(PPCHIRBuilder& f, InstrData& i) { return 1; } Value* v = f.Mul( - f.ZeroExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE), - f.ZeroExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE)); + f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RA), INT32_TYPE), INT64_TYPE), + f.SignExtend(f.Truncate(f.LoadGPR(i.XO.RB), INT32_TYPE), INT64_TYPE)); f.StoreGPR(i.XO.RT, v); if (i.XO.Rc) { f.UpdateCR(0, v); diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhd.bin b/src/alloy/frontend/ppc/test/bin/instr_mulhd.bin new file mode 100644 index 0000000000000000000000000000000000000000..7b4ce8e351a78549851afb14c3e2ed4bad60d30f GIT binary patch literal 40 Scmb: + 100000: 7c 64 28 92 mulhd r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 64 28 92 mulhd r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 64 28 92 mulhd r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 28 92 mulhd r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 64 28 92 mulhd r3,r4,r5 + 100024: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhd.map b/src/alloy/frontend/ppc/test/bin/instr_mulhd.map new file mode 100644 index 000000000..3699fc0f3 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulhd.map @@ -0,0 +1,5 @@ +0000000000000000 t test_mulhd_1 +0000000000000008 t test_mulhd_2 +0000000000000010 t test_mulhd_3 +0000000000000018 t test_mulhd_4 +0000000000000020 t test_mulhd_5 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhdu.bin b/src/alloy/frontend/ppc/test/bin/instr_mulhdu.bin new file mode 100644 index 0000000000000000000000000000000000000000..9710b2b7805469776e6a05ea43193487077ae410 GIT binary patch literal 40 Scmb: + 100000: 7c 64 28 12 mulhdu r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 64 28 12 mulhdu r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 64 28 12 mulhdu r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 28 12 mulhdu r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 64 28 12 mulhdu r3,r4,r5 + 100024: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhdu.map b/src/alloy/frontend/ppc/test/bin/instr_mulhdu.map new file mode 100644 index 000000000..52d4039b0 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulhdu.map @@ -0,0 +1,5 @@ +0000000000000000 t test_mulhdu_1 +0000000000000008 t test_mulhdu_2 +0000000000000010 t test_mulhdu_3 +0000000000000018 t test_mulhdu_4 +0000000000000020 t test_mulhdu_5 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhw.bin b/src/alloy/frontend/ppc/test/bin/instr_mulhw.bin new file mode 100644 index 0000000000000000000000000000000000000000..1a38c4ccde837bfd61b85ebca917c6e0bc52d52d GIT binary patch literal 48 Scmb: + 100000: 7c 64 28 96 mulhw r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 64 28 96 mulhw r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 64 28 96 mulhw r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 28 96 mulhw r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 64 28 96 mulhw r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 64 28 96 mulhw r3,r4,r5 + 10002c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhw.map b/src/alloy/frontend/ppc/test/bin/instr_mulhw.map new file mode 100644 index 000000000..5699dda49 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulhw.map @@ -0,0 +1,6 @@ +0000000000000000 t test_mulhw_1 +0000000000000008 t test_mulhw_2 +0000000000000010 t test_mulhw_3 +0000000000000018 t test_mulhw_4 +0000000000000020 t test_mulhw_5 +0000000000000028 t test_mulhw_6 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhwu.bin b/src/alloy/frontend/ppc/test/bin/instr_mulhwu.bin new file mode 100644 index 0000000000000000000000000000000000000000..db45968054ba49ccef032b76df19c28716fd40f9 GIT binary patch literal 48 Scmb: + 100000: 7c 64 28 16 mulhwu r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 64 28 16 mulhwu r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 64 28 16 mulhwu r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 28 16 mulhwu r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 64 28 16 mulhwu r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 64 28 16 mulhwu r3,r4,r5 + 10002c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulhwu.map b/src/alloy/frontend/ppc/test/bin/instr_mulhwu.map new file mode 100644 index 000000000..2c8ddc055 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulhwu.map @@ -0,0 +1,6 @@ +0000000000000000 t test_mulhwu_1 +0000000000000008 t test_mulhwu_2 +0000000000000010 t test_mulhwu_3 +0000000000000018 t test_mulhwu_4 +0000000000000020 t test_mulhwu_5 +0000000000000028 t test_mulhwu_6 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulld.bin b/src/alloy/frontend/ppc/test/bin/instr_mulld.bin new file mode 100644 index 0000000000000000000000000000000000000000..e93d7cac1d626fc909d6fd9f2f4692130949b83e GIT binary patch literal 64 Scmbz@Sh=CJg}OUKU9J literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulld.dis b/src/alloy/frontend/ppc/test/bin/instr_mulld.dis new file mode 100644 index 000000000..f1df8455c --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulld.dis @@ -0,0 +1,37 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulld.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 7c 64 29 d2 mulld r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 64 29 d2 mulld r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 64 29 d2 mulld r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 29 d2 mulld r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 64 29 d2 mulld r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 64 29 d2 mulld r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 64 29 d2 mulld r3,r4,r5 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 7c 64 29 d2 mulld r3,r4,r5 + 10003c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulld.map b/src/alloy/frontend/ppc/test/bin/instr_mulld.map new file mode 100644 index 000000000..45aac1f83 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulld.map @@ -0,0 +1,8 @@ +0000000000000000 t test_mulld_1 +0000000000000008 t test_mulld_2 +0000000000000010 t test_mulld_3 +0000000000000018 t test_mulld_4 +0000000000000020 t test_mulld_5 +0000000000000028 t test_mulld_6 +0000000000000030 t test_mulld_7 +0000000000000038 t test_mulld_8 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulli.bin b/src/alloy/frontend/ppc/test/bin/instr_mulli.bin new file mode 100644 index 0000000000000000000000000000000000000000..e9038f7ac9b66672a6e30d8a400e4579813da5f1 GIT binary patch literal 64 gcmb11VPNoUU{H`rVPJ&N|No=XFmVPZRB?zp06*>%Z2$lO literal 0 HcmV?d00001 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulli.dis b/src/alloy/frontend/ppc/test/bin/instr_mulli.dis new file mode 100644 index 000000000..716cefe73 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulli.dis @@ -0,0 +1,37 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_mulli.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 1c 64 00 00 mulli r3,r4,0 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 1c 64 00 01 mulli r3,r4,1 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 1c 64 ff ff mulli r3,r4,-1 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 1c 64 ff ff mulli r3,r4,-1 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 1c 64 00 01 mulli r3,r4,1 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 1c 64 00 02 mulli r3,r4,2 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 1c 64 ff ff mulli r3,r4,-1 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 1c 64 ff ff mulli r3,r4,-1 + 10003c: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mulli.map b/src/alloy/frontend/ppc/test/bin/instr_mulli.map new file mode 100644 index 000000000..e173e7d9d --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mulli.map @@ -0,0 +1,8 @@ +0000000000000000 t test_mulli_1 +0000000000000008 t test_mulli_2 +0000000000000010 t test_mulli_3 +0000000000000018 t test_mulli_4 +0000000000000020 t test_mulli_5 +0000000000000028 t test_mulli_6 +0000000000000030 t test_mulli_7 +0000000000000038 t test_mulli_8 diff --git a/src/alloy/frontend/ppc/test/bin/instr_mullw.bin b/src/alloy/frontend/ppc/test/bin/instr_mullw.bin new file mode 100644 index 0000000000000000000000000000000000000000..f74ec3f83bb74eb2a5f394f4944ba4e5606c0f69 GIT binary patch literal 88 Scmb: + 100000: 7c 64 29 d6 mullw r3,r4,r5 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 7c 64 29 d6 mullw r3,r4,r5 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 7c 64 29 d6 mullw r3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 29 d6 mullw r3,r4,r5 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 7c 64 29 d6 mullw r3,r4,r5 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 64 29 d6 mullw r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 64 29 d6 mullw r3,r4,r5 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 7c 64 29 d6 mullw r3,r4,r5 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 7c 64 29 d6 mullw r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 29 d6 mullw r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 7c 64 29 d6 mullw r3,r4,r5 + 100054: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_mullw.map b/src/alloy/frontend/ppc/test/bin/instr_mullw.map new file mode 100644 index 000000000..6b1f69085 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_mullw.map @@ -0,0 +1,11 @@ +0000000000000000 t test_mullw_1 +0000000000000008 t test_mullw_2 +0000000000000010 t test_mullw_3 +0000000000000018 t test_mullw_4 +0000000000000020 t test_mullw_5 +0000000000000028 t test_mullw_6 +0000000000000030 t test_mullw_7 +0000000000000038 t test_mullw_8 +0000000000000040 t test_mullw_9 +0000000000000048 t test_mullw_10 +0000000000000050 t test_mullw_11 diff --git a/src/alloy/frontend/ppc/test/instr_mulhd.s b/src/alloy/frontend/ppc/test/instr_mulhd.s new file mode 100644 index 000000000..883b28b71 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mulhd.s @@ -0,0 +1,44 @@ +test_mulhd_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + mulhd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_mulhd_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + mulhd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhd_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 2 + mulhd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 2 + +test_mulhd_4: + #_ REGISTER_IN r4 0x8000000000000000 + #_ REGISTER_IN r5 1 + mulhd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x8000000000000000 + #_ REGISTER_OUT r5 1 + +test_mulhd_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhd r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF diff --git a/src/alloy/frontend/ppc/test/instr_mulhdu.s b/src/alloy/frontend/ppc/test/instr_mulhdu.s new file mode 100644 index 000000000..d57ae0ade --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mulhdu.s @@ -0,0 +1,44 @@ +test_mulhdu_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + mulhdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_mulhdu_2: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + mulhdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhdu_3: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 2 + mulhdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 2 + +test_mulhdu_4: + #_ REGISTER_IN r4 0x8000000000000000 + #_ REGISTER_IN r5 1 + mulhdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0x8000000000000000 + #_ REGISTER_OUT r5 1 + +test_mulhdu_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF diff --git a/src/alloy/frontend/ppc/test/instr_mulhw.s b/src/alloy/frontend/ppc/test/instr_mulhw.s new file mode 100644 index 000000000..08247344c --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mulhw.s @@ -0,0 +1,53 @@ +test_mulhw_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + mulhw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_mulhw_2: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 1 + mulhw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhw_3: + #_ REGISTER_IN r4 0x00000001FFFFFFFF + #_ REGISTER_IN r5 1 + mulhw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0x00000001FFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhw_4: + #_ REGISTER_IN r4 0x800000007FFFFFFF + #_ REGISTER_IN r5 1 + mulhw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0x800000007FFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhw_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + mulhw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhw_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF diff --git a/src/alloy/frontend/ppc/test/instr_mulhwu.s b/src/alloy/frontend/ppc/test/instr_mulhwu.s new file mode 100644 index 000000000..eb838afe2 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mulhwu.s @@ -0,0 +1,53 @@ +test_mulhwu_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + mulhwu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_mulhwu_2: + #_ REGISTER_IN r4 0x00000000FFFFFFFF + #_ REGISTER_IN r5 1 + mulhwu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0x00000000FFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhwu_3: + #_ REGISTER_IN r4 0x00000001FFFFFFFF + #_ REGISTER_IN r5 1 + mulhwu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0x00000001FFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhwu_4: + #_ REGISTER_IN r4 0x800000007FFFFFFF + #_ REGISTER_IN r5 1 + mulhwu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0x800000007FFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhwu_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + mulhwu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulhwu_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF + mulhwu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x00000000FFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF diff --git a/src/alloy/frontend/ppc/test/instr_mulld.s b/src/alloy/frontend/ppc/test/instr_mulld.s new file mode 100644 index 000000000..89e38c0f3 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mulld.s @@ -0,0 +1,72 @@ +test_mulld_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_mulld_2: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 1 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 1 + +test_mulld_3: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 -1 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 -1 + +test_mulld_4: + #_ REGISTER_IN r4 123 + #_ REGISTER_IN r5 -1 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 -123 + #_ REGISTER_OUT r4 123 + #_ REGISTER_OUT r5 -1 + +test_mulld_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mulld_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 2 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 2 + +test_mulld_7: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 -1 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 -1 + +test_mulld_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 -1 + mulld r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 -1 + diff --git a/src/alloy/frontend/ppc/test/instr_mulli.s b/src/alloy/frontend/ppc/test/instr_mulli.s new file mode 100644 index 000000000..92b5ae9ef --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mulli.s @@ -0,0 +1,56 @@ +test_mulli_1: + #_ REGISTER_IN r4 1 + mulli r3, r4, 0 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + +test_mulli_2: + #_ REGISTER_IN r4 1 + mulli r3, r4, 1 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + +test_mulli_3: + #_ REGISTER_IN r4 1 + mulli r3, r4, -1 + blr + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 1 + +test_mulli_4: + #_ REGISTER_IN r4 123 + mulli r3, r4, -1 + blr + #_ REGISTER_OUT r3 -123 + #_ REGISTER_OUT r4 123 + +test_mulli_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + mulli r3, r4, 1 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_mulli_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + mulli r3, r4, 2 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + +test_mulli_7: + #_ REGISTER_IN r4 1 + mulli r3, r4, -1 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 1 + +test_mulli_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + mulli r3, r4, -1 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + diff --git a/src/alloy/frontend/ppc/test/instr_mullw.s b/src/alloy/frontend/ppc/test/instr_mullw.s new file mode 100644 index 000000000..926ef66c0 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_mullw.s @@ -0,0 +1,99 @@ +test_mullw_1: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0 + +test_mullw_2: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 1 + +test_mullw_3: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 -1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 -1 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 -1 + +test_mullw_4: + #_ REGISTER_IN r4 123 + #_ REGISTER_IN r5 -1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 -123 + #_ REGISTER_OUT r4 123 + #_ REGISTER_OUT r5 -1 + +test_mullw_5: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 1 + +test_mullw_6: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 2 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFE + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 2 + +test_mullw_7: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 -1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 -1 + +test_mullw_8: + #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_IN r5 -1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 1 + #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF + #_ REGISTER_OUT r5 -1 + +test_mullw_9: + #_ REGISTER_IN r4 0xFFFFFFFF00000000 + #_ REGISTER_IN r5 1 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0xFFFFFFFF00000000 + #_ REGISTER_OUT r5 1 + +test_mullw_10: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0xFFFFFFFF00000000 + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0xFFFFFFFF00000000 + +test_mullw_11: + #_ REGISTER_IN r4 1 + #_ REGISTER_IN r5 0x000000007FFFFFFF + mullw r3, r4, r5 + blr + #_ REGISTER_OUT r3 0x000000007FFFFFFF + #_ REGISTER_OUT r4 1 + #_ REGISTER_OUT r5 0x000000007FFFFFFF +