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Removing unused HIR opcodes. 

Progress on #291.
This commit is contained in:
Ben Vanik 2015-06-28 10:53:32 -07:00
parent 3745746fcc
commit 0630b524fa
6 changed files with 2 additions and 77 deletions
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20
src/xenia/cpu/backend/x64/x64_sequences.cc
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@ -6525,11 +6525,6 @@ EMITTER_OPCODE_TABLE(
UNPACK); UNPACK);
// ============================================================================
// OPCODE_COMPARE_EXCHANGE
// ============================================================================
// ============================================================================ // ============================================================================
// OPCODE_ATOMIC_EXCHANGE // OPCODE_ATOMIC_EXCHANGE
// ============================================================================ // ============================================================================
@ -6588,18 +6583,6 @@ EMITTER_OPCODE_TABLE(
ATOMIC_EXCHANGE_I64); ATOMIC_EXCHANGE_I64);
// ============================================================================
// OPCODE_ATOMIC_ADD
// ============================================================================
// ============================================================================
// OPCODE_ATOMIC_SUB
// ============================================================================
//SEQUENCE(ADD_ADD_BRANCH, MATCH( //SEQUENCE(ADD_ADD_BRANCH, MATCH(
// I<OPCODE_ADD, I32<TAG0>, I32<>, I32C<>>, // I<OPCODE_ADD, I32<TAG0>, I32<>, I32C<>>,
// I<OPCODE_ADD, I32<>, I32<TAG0>, I32C<>>, // I<OPCODE_ADD, I32<>, I32<TAG0>, I32C<>>,
@ -6723,10 +6706,7 @@ void RegisterSequences() {
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_SWIZZLE); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_SWIZZLE);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_PACK); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_PACK);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_UNPACK); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_UNPACK);
//REGISTER_EMITTER_OPCODE_TABLE(OPCODE_COMPARE_EXCHANGE);
REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_EXCHANGE); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_EXCHANGE);
//REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_ADD);
//REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_SUB);
} }
bool SelectSequence(X64Emitter& e, const Instr* i, const Instr** new_tail) { bool SelectSequence(X64Emitter& e, const Instr* i, const Instr** new_tail) {

34
src/xenia/cpu/hir/hir_builder.cc
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@ -2059,20 +2059,6 @@ Value* HIRBuilder::Unpack(Value* value, uint32_t pack_flags) {
return i->dest; return i->dest;
} }
Value* HIRBuilder::CompareExchange(Value* address, Value* compare_value,
Value* exchange_value) {
ASSERT_ADDRESS_TYPE(address);
ASSERT_INTEGER_TYPE(compare_value);
ASSERT_INTEGER_TYPE(exchange_value);
ASSERT_TYPES_EQUAL(compare_value, exchange_value);
Instr* i = AppendInstr(OPCODE_COMPARE_EXCHANGE_info, 0,
AllocValue(exchange_value->type));
i->set_src1(address);
i->set_src2(compare_value);
i->set_src3(exchange_value);
return i->dest;
}
Value* HIRBuilder::AtomicExchange(Value* address, Value* new_value) { Value* HIRBuilder::AtomicExchange(Value* address, Value* new_value) {
ASSERT_ADDRESS_TYPE(address); ASSERT_ADDRESS_TYPE(address);
ASSERT_INTEGER_TYPE(new_value); ASSERT_INTEGER_TYPE(new_value);
@ -2084,26 +2070,6 @@ Value* HIRBuilder::AtomicExchange(Value* address, Value* new_value) {
return i->dest; return i->dest;
} }
Value* HIRBuilder::AtomicAdd(Value* address, Value* value) {
ASSERT_ADDRESS_TYPE(address);
ASSERT_INTEGER_TYPE(value);
Instr* i = AppendInstr(OPCODE_ATOMIC_ADD_info, 0, AllocValue(value->type));
i->set_src1(address);
i->set_src2(value);
i->src3.value = NULL;
return i->dest;
}
Value* HIRBuilder::AtomicSub(Value* address, Value* value) {
ASSERT_ADDRESS_TYPE(address);
ASSERT_INTEGER_TYPE(value);
Instr* i = AppendInstr(OPCODE_ATOMIC_SUB_info, 0, AllocValue(value->type));
i->set_src1(address);
i->set_src2(value);
i->src3.value = NULL;
return i->dest;
}
} // namespace hir } // namespace hir
} // namespace cpu } // namespace cpu
} // namespace xe } // namespace xe

2
src/xenia/cpu/hir/hir_builder.h
View File

@ -234,8 +234,6 @@ class HIRBuilder {
Value* Pack(Value* value1, Value* value2, uint32_t pack_flags = 0); Value* Pack(Value* value1, Value* value2, uint32_t pack_flags = 0);
Value* Unpack(Value* value, uint32_t pack_flags = 0); Value* Unpack(Value* value, uint32_t pack_flags = 0);
Value* CompareExchange(Value* address, Value* compare_value,
Value* exchange_value);
Value* AtomicExchange(Value* address, Value* new_value); Value* AtomicExchange(Value* address, Value* new_value);
Value* AtomicAdd(Value* address, Value* value); Value* AtomicAdd(Value* address, Value* value);
Value* AtomicSub(Value* address, Value* value); Value* AtomicSub(Value* address, Value* value);

2
src/xenia/cpu/hir/opcodes.cc
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@ -9,6 +9,8 @@
#include "xenia/cpu/hir/opcodes.h" #include "xenia/cpu/hir/opcodes.h"
using namespace xe::cpu::hir;
namespace xe { namespace xe {
namespace cpu { namespace cpu {
namespace hir { namespace hir {

3
src/xenia/cpu/hir/opcodes.h
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@ -200,10 +200,7 @@ enum Opcode {
OPCODE_SWIZZLE, OPCODE_SWIZZLE,
OPCODE_PACK, OPCODE_PACK,
OPCODE_UNPACK, OPCODE_UNPACK,
OPCODE_COMPARE_EXCHANGE,
OPCODE_ATOMIC_EXCHANGE, OPCODE_ATOMIC_EXCHANGE,
OPCODE_ATOMIC_ADD,
OPCODE_ATOMIC_SUB,
__OPCODE_MAX_VALUE, // Keep at end. __OPCODE_MAX_VALUE, // Keep at end.
}; };

18
src/xenia/cpu/hir/opcodes.inl
View File

@ -614,26 +614,8 @@ DEFINE_OPCODE(
OPCODE_SIG_V_V, OPCODE_SIG_V_V,
0) 0)
DEFINE_OPCODE(
OPCODE_COMPARE_EXCHANGE,
"compare_exchange",
OPCODE_SIG_V_V_V_V,
OPCODE_FLAG_VOLATILE)
DEFINE_OPCODE( DEFINE_OPCODE(
OPCODE_ATOMIC_EXCHANGE, OPCODE_ATOMIC_EXCHANGE,
"atomic_exchange", "atomic_exchange",
OPCODE_SIG_V_V_V, OPCODE_SIG_V_V_V,
OPCODE_FLAG_VOLATILE) OPCODE_FLAG_VOLATILE)
DEFINE_OPCODE(
OPCODE_ATOMIC_ADD,
"atomic_add",
OPCODE_SIG_V_V_V,
0)
DEFINE_OPCODE(
OPCODE_ATOMIC_SUB,
"atomic_sub",
OPCODE_SIG_V_V_V,
0)