From 0630b524fa9452ac01b8b6178b3d8ce641049df3 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sun, 28 Jun 2015 10:53:32 -0700 Subject: [PATCH] Removing unused HIR opcodes. Progress on #291. --- src/xenia/cpu/backend/x64/x64_sequences.cc | 20 ------------- src/xenia/cpu/hir/hir_builder.cc | 34 ---------------------- src/xenia/cpu/hir/hir_builder.h | 2 -- src/xenia/cpu/hir/opcodes.cc | 2 ++ src/xenia/cpu/hir/opcodes.h | 3 -- src/xenia/cpu/hir/opcodes.inl | 18 ------------ 6 files changed, 2 insertions(+), 77 deletions(-) diff --git a/src/xenia/cpu/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc index 400e6a7f5..575d89a81 100644 --- a/src/xenia/cpu/backend/x64/x64_sequences.cc +++ b/src/xenia/cpu/backend/x64/x64_sequences.cc @@ -6525,11 +6525,6 @@ EMITTER_OPCODE_TABLE( UNPACK); -// ============================================================================ -// OPCODE_COMPARE_EXCHANGE -// ============================================================================ - - // ============================================================================ // OPCODE_ATOMIC_EXCHANGE // ============================================================================ @@ -6588,18 +6583,6 @@ EMITTER_OPCODE_TABLE( ATOMIC_EXCHANGE_I64); -// ============================================================================ -// OPCODE_ATOMIC_ADD -// ============================================================================ - - -// ============================================================================ -// OPCODE_ATOMIC_SUB -// ============================================================================ - - - - //SEQUENCE(ADD_ADD_BRANCH, MATCH( // I, I32<>, I32C<>>, // I, I32, I32C<>>, @@ -6723,10 +6706,7 @@ void RegisterSequences() { REGISTER_EMITTER_OPCODE_TABLE(OPCODE_SWIZZLE); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_PACK); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_UNPACK); - //REGISTER_EMITTER_OPCODE_TABLE(OPCODE_COMPARE_EXCHANGE); REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_EXCHANGE); - //REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_ADD); - //REGISTER_EMITTER_OPCODE_TABLE(OPCODE_ATOMIC_SUB); } bool SelectSequence(X64Emitter& e, const Instr* i, const Instr** new_tail) { diff --git a/src/xenia/cpu/hir/hir_builder.cc b/src/xenia/cpu/hir/hir_builder.cc index eac335d64..000a5ce10 100644 --- a/src/xenia/cpu/hir/hir_builder.cc +++ b/src/xenia/cpu/hir/hir_builder.cc @@ -2059,20 +2059,6 @@ Value* HIRBuilder::Unpack(Value* value, uint32_t pack_flags) { return i->dest; } -Value* HIRBuilder::CompareExchange(Value* address, Value* compare_value, - Value* exchange_value) { - ASSERT_ADDRESS_TYPE(address); - ASSERT_INTEGER_TYPE(compare_value); - ASSERT_INTEGER_TYPE(exchange_value); - ASSERT_TYPES_EQUAL(compare_value, exchange_value); - Instr* i = AppendInstr(OPCODE_COMPARE_EXCHANGE_info, 0, - AllocValue(exchange_value->type)); - i->set_src1(address); - i->set_src2(compare_value); - i->set_src3(exchange_value); - return i->dest; -} - Value* HIRBuilder::AtomicExchange(Value* address, Value* new_value) { ASSERT_ADDRESS_TYPE(address); ASSERT_INTEGER_TYPE(new_value); @@ -2084,26 +2070,6 @@ Value* HIRBuilder::AtomicExchange(Value* address, Value* new_value) { return i->dest; } -Value* HIRBuilder::AtomicAdd(Value* address, Value* value) { - ASSERT_ADDRESS_TYPE(address); - ASSERT_INTEGER_TYPE(value); - Instr* i = AppendInstr(OPCODE_ATOMIC_ADD_info, 0, AllocValue(value->type)); - i->set_src1(address); - i->set_src2(value); - i->src3.value = NULL; - return i->dest; -} - -Value* HIRBuilder::AtomicSub(Value* address, Value* value) { - ASSERT_ADDRESS_TYPE(address); - ASSERT_INTEGER_TYPE(value); - Instr* i = AppendInstr(OPCODE_ATOMIC_SUB_info, 0, AllocValue(value->type)); - i->set_src1(address); - i->set_src2(value); - i->src3.value = NULL; - return i->dest; -} - } // namespace hir } // namespace cpu } // namespace xe diff --git a/src/xenia/cpu/hir/hir_builder.h b/src/xenia/cpu/hir/hir_builder.h index faa10bc12..ce1119b74 100644 --- a/src/xenia/cpu/hir/hir_builder.h +++ b/src/xenia/cpu/hir/hir_builder.h @@ -234,8 +234,6 @@ class HIRBuilder { Value* Pack(Value* value1, Value* value2, uint32_t pack_flags = 0); Value* Unpack(Value* value, uint32_t pack_flags = 0); - Value* CompareExchange(Value* address, Value* compare_value, - Value* exchange_value); Value* AtomicExchange(Value* address, Value* new_value); Value* AtomicAdd(Value* address, Value* value); Value* AtomicSub(Value* address, Value* value); diff --git a/src/xenia/cpu/hir/opcodes.cc b/src/xenia/cpu/hir/opcodes.cc index bbfe0cebe..0e4ae6ffd 100644 --- a/src/xenia/cpu/hir/opcodes.cc +++ b/src/xenia/cpu/hir/opcodes.cc @@ -9,6 +9,8 @@ #include "xenia/cpu/hir/opcodes.h" +using namespace xe::cpu::hir; + namespace xe { namespace cpu { namespace hir { diff --git a/src/xenia/cpu/hir/opcodes.h b/src/xenia/cpu/hir/opcodes.h index ceeb3cca9..99d34ab5d 100644 --- a/src/xenia/cpu/hir/opcodes.h +++ b/src/xenia/cpu/hir/opcodes.h @@ -200,10 +200,7 @@ enum Opcode { OPCODE_SWIZZLE, OPCODE_PACK, OPCODE_UNPACK, - OPCODE_COMPARE_EXCHANGE, OPCODE_ATOMIC_EXCHANGE, - OPCODE_ATOMIC_ADD, - OPCODE_ATOMIC_SUB, __OPCODE_MAX_VALUE, // Keep at end. }; diff --git a/src/xenia/cpu/hir/opcodes.inl b/src/xenia/cpu/hir/opcodes.inl index 6c1c724e7..68d182223 100644 --- a/src/xenia/cpu/hir/opcodes.inl +++ b/src/xenia/cpu/hir/opcodes.inl @@ -614,26 +614,8 @@ DEFINE_OPCODE( OPCODE_SIG_V_V, 0) -DEFINE_OPCODE( - OPCODE_COMPARE_EXCHANGE, - "compare_exchange", - OPCODE_SIG_V_V_V_V, - OPCODE_FLAG_VOLATILE) - DEFINE_OPCODE( OPCODE_ATOMIC_EXCHANGE, "atomic_exchange", OPCODE_SIG_V_V_V, OPCODE_FLAG_VOLATILE) - -DEFINE_OPCODE( - OPCODE_ATOMIC_ADD, - "atomic_add", - OPCODE_SIG_V_V_V, - 0) - -DEFINE_OPCODE( - OPCODE_ATOMIC_SUB, - "atomic_sub", - OPCODE_SIG_V_V_V, - 0)