xemu/target
Daniel Henrique Barboza 1770b2f2d3 accel/tcg: Add 'size' param to probe_access_flags()
probe_access_flags() as it is today uses probe_access_full(), which in
turn uses probe_access_internal() with size = 0. probe_access_internal()
then uses the size to call the tlb_fill() callback for the given CPU.
This size param ('fault_size' as probe_access_internal() calls it) is
ignored by most existing .tlb_fill callback implementations, e.g.
arm_cpu_tlb_fill(), ppc_cpu_tlb_fill(), x86_cpu_tlb_fill() and
mips_cpu_tlb_fill() to name a few.

But RISC-V riscv_cpu_tlb_fill() actually uses it. The 'size' parameter
is used to check for PMP (Physical Memory Protection) access. This is
necessary because PMP does not make any guarantees about all the bytes
of the same page having the same permissions, i.e. the same page can
have different PMP properties, so we're forced to make sub-page range
checks. To allow RISC-V emulation to do a probe_acess_flags() that
covers PMP, we need to either add a 'size' param to the existing
probe_acess_flags() or create a new interface (e.g.
probe_access_range_flags).

There are quite a few probe_* APIs already, so let's add a 'size' param
to probe_access_flags() and re-use this API. This is done by open coding
what probe_access_full() does inside probe_acess_flags() and passing the
'size' param to probe_acess_internal(). Existing probe_access_flags()
callers use size = 0 to not change their current API usage. 'size' is
asserted to enforce single page access like probe_access() already does.

No behavioral changes intended.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230223234427.521114-2-dbarboza@ventanamicro.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-02-28 10:32:31 -10:00
..
alpha target/alpha: Remove obsolete STATUS document 2023-02-27 22:29:01 +01:00
arm accel/tcg: Add 'size' param to probe_access_flags() 2023-02-28 10:32:31 -10:00
avr target/avr: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
cris target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu 2023-02-27 22:29:01 +01:00
hexagon target/hexagon: Clean up includes 2023-02-08 07:28:05 +01:00
hppa target/hppa: Extract system helpers to sys_helper.c 2023-02-27 22:29:01 +01:00
i386 - buildsys 2023-02-28 15:09:18 +00:00
loongarch target/loongarch/cpu: Restrict "memory.h" header to sysemu 2023-02-27 22:29:01 +01:00
m68k target/cpu: Restrict do_transaction_failed() handlers to sysemu 2023-02-27 22:29:01 +01:00
microblaze target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu 2023-02-27 22:29:01 +01:00
mips Drop duplicate #include 2023-02-08 07:28:05 +01:00
nios2 target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu 2023-02-27 22:29:01 +01:00
openrisc target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu 2023-02-27 22:29:01 +01:00
ppc target/ppc: Fix warning with clang-15 2023-02-27 22:29:01 +01:00
riscv target/riscv/cpu: Move Floating-Point fields closer 2023-02-27 22:29:01 +01:00
rx target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu 2023-02-27 22:29:01 +01:00
s390x accel/tcg: Add 'size' param to probe_access_flags() 2023-02-28 10:32:31 -10:00
sh4 target/cpu: Restrict cpu_get_phys_page_debug() handlers to sysemu 2023-02-27 22:29:01 +01:00
sparc target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard 2023-02-27 22:29:01 +01:00
tricore target/tricore: Remove unused fields from CPUTriCoreState 2023-02-27 22:29:01 +01:00
xtensa target/xtensa/cpu: Include missing "memory.h" header 2023-02-27 22:29:01 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00