xemu/target/i386/tcg
Paolo Bonzini 16fc5726a6 target/i386: reimplement 0x0f 0x38, add AVX
There are several special cases here:

1) extending moves have different widths for the helpers vs. for the
memory loads, and the width for memory loads depends on VEX.L too.
This is represented by X86_SPECIAL_AVXExtMov.

2) some instructions, such as variable-width shifts, select the vector element
size via REX.W.

3) VSIB instructions (VGATHERxPy, VPGATHERxy) are also part of this group,
and they have (among other things) two output operands.

3) the macros for 4-operand blends (which are under 0x0f 0x3a) have to be
extended to support 2-operand blends.  The 2-operand variant actually
came a few years earlier, but it is clearer to implement them in the
opposite order.

X86_TYPE_WM, introduced earlier for unaligned loads, is reused for helpers
that accept a Reg* but have a M argument.

These three-byte opcodes also include AVX new instructions, for which
the helpers were originally implemented by Paul Brook <paul@nowt.org>.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2022-10-18 13:58:05 +02:00
..
sysemu target/i386: Use probe_access_full for final stage2 translation 2022-10-18 13:58:04 +02:00
user target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
bpt_helper.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
cc_helper.c i386: move TCG cpu class initialization to tcg/ 2020-12-16 15:50:33 -05:00
cc_helper_template.h i386: move TCG accel files into tcg/ 2020-12-16 14:06:53 -05:00
decode-new.c.inc target/i386: reimplement 0x0f 0x38, add AVX 2022-10-18 13:58:05 +02:00
decode-new.h target/i386: reimplement 0x0f 0x38, add AVX 2022-10-18 13:58:05 +02:00
emit.c.inc target/i386: reimplement 0x0f 0x38, add AVX 2022-10-18 13:58:05 +02:00
excp_helper.c target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
fpu_helper.c target/i386: Introduce 256-bit vector helpers 2022-10-18 13:58:04 +02:00
helper-tcg.h target/i386: Raise #GP on unaligned m128 accesses when required. 2022-09-18 09:17:40 +02:00
int_helper.c exec/exec-all: Move 'qemu/log.h' include in units requiring it 2022-02-21 10:18:06 +01:00
mem_helper.c exec/memop: Adding signedness to quad definitions 2022-01-08 15:46:10 +10:00
meson.build i386: split svm_helper into sysemu and stub-only user 2021-05-10 15:41:51 -04:00
misc_helper.c compiler.h: replace QEMU_NORETURN with G_NORETURN 2022-04-21 17:03:51 +04:00
mpx_helper.c i386: move TCG cpu class initialization to tcg/ 2020-12-16 15:50:33 -05:00
seg_helper.c target/i386: Truncate values for lcall_real to i32 2022-10-11 09:36:01 +02:00
seg_helper.h i386: split seg_helper into user-only and sysemu parts 2021-05-10 15:41:52 -04:00
tcg-cpu.c target/i386: Enable TARGET_TB_PCREL 2022-10-11 09:36:01 +02:00
tcg-cpu.h target/i386: Move X86XSaveArea into TCG 2021-07-06 08:33:51 +02:00
tcg-stub.c i386: move TCG accel files into tcg/ 2020-12-16 14:06:53 -05:00
translate.c target/i386: reimplement 0x0f 0x38, add AVX 2022-10-18 13:58:05 +02:00